Dongbu Hitek Co., Ltd.

Hynix Semiconductor Inc.

Sang Wook Ryu

Jin Ho Park

Ki Jun Yun

Oh Jin Jung

Seong Hun Jeong

Kang Sup Shin

Chung Kyung Jung

Sung Wook Joo

Man Ghil Han

Method for manufacturing a semiconductor device includes the steps of forming a lower electrode pattern on a substrate, forming a first interlayer insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first interlayer insulating layer, forming a second interlayer insulating layer on the upper electrode pattern, forming an etch blocking layer on a side of the upper electrode pattern, wherein the etch blocking layer passes through the first interlayer insulating layer, forming a cavity which exposes the side of the etch blocking layer by etching the second interlayer insulating layer, and forming a contact ball in the cavity.

Semiconductor device and method for manufacturing the same

A metal interconnection of semiconductor device and method for fabricating the same is provided. The semiconductor device can include a semiconductor substrate formed with device structures such as transistors. An interlayer dielectric layer can be formed on the semiconductor substrate with a metal interconnection formed therethrough. A spacer can be formed on at least a portion of a sidewall of the metal interconnection. A diffusion barrier can be formed on an upper surface of the metal interconnection.

Semiconductor device and method of manufacturing the same

An image sensor and method of manufacturing thereof are provided. In an embodiment, an image sensor can include a photodiode on a substrate, an interlayer dielectric formed on the substrate, an insulating layer micro-lens on the interlayer dielectric, and an organic micro-lens on the insulating layer micro-lens.

Image sensor and method for manufacturing the same

A method for forming a trench isolation in a semiconductor device is provided. This is a novel method for rounding the top corners of trench isolations. The method ensures that rounded corner portions with a uniform shape are consistently formed regardless of the pattern densities of active areas. The method increases the reliability of semiconductor integrated circuit devices, without degrading electrical characteristics, and making it easier to achieve high integration and performance in semiconductor integrated circuit devices.

Method for forming trench isolation

An image sensor and method for manufacturing the same are provided. The image sensor can include a semiconductor substrate, a metal interconnection layer, a light-receiving unit, a lens-type upper electrode, and a color filter. The semiconductor substrate can include a circuit region. The metal interconnection layer can include a metal interconnection and an interlayer dielectric. The light-receiving unit can be a photodiode disposed on the metal interconnection layer. The lens-type upper electrode can be disposed on the light-receiving unit and formed in a convex lens shape. The color filter can be disposed on the lens-type upper electrode.

Image sensor and method of manufacturing the same

A method for manufacturing an image sensor according to an embodiment includes performing a plasma surface treatment on an oxide film microlens to mitigate high surface morphology. The image sensor can include a passivation layer on a substrate having a pad region and a pixel region and a color filter layer on the passivation layer. A first low temperature oxide can be formed over the substrate including the color filter layer; and an oxide film microlens can be formed on the first low temperature oxide layer. A portion of the first low temperature oxide layer can provide a seed microlens upon which a second low temperature oxide layer is formed to form the oxide film microlenses. The plasma surface treatment can then be applied with respect to the oxide film microlenses.

Method for manufacturing image sensor

Methods for forming a contact hole in a semiconductor device are provided. An exposed portion of an isolation layer, which may be generated during a process of forming a borderless contact hole, can be covered with a material similar to that of the substrate.

Method for forming contact hole in semiconductor device

The present invention discloses a method for forming an interlayer insulation film in a semiconductor device, comprising the steps of: sequentially forming a porous low dielectric insulation film and a capping layer on the semiconductor substrate on which a few elements of the semiconductor device have been formed; and forming damascene patterns in the porous low dielectric insulation film by an etching process, and forming a protection film for closing pores exposed during the etching process at the same time.

Method for forming interlayer insulation film in semiconductor device

The present invention relates to a method of forming a metal line in a semiconductor device, in which an etch-stopping layer is deposited between the interlayer insulation films and then over-etching is performed by using the etch-stopping layer as an etching barrier during the etching process for forming the subsequent trenches. Therefore, it is possible to restrain occurrence of parasitic spacers in the trenches.

Method of forming metal line in semiconductor device

A method is provided for forming a conductive wire of a semiconductor device using, for example, a damascene process. A conductive wire, such as a metal wire, is formed, based on a notching phenomenon which occurs when the etching selectivity between a polycrystalline silicon layer and a lower film is approximately 5 to 500:1.

Method for forming T-shaped conductor wires of semiconductor device

The present invention is provided to form a trench in a semiconductor device, wherein by performing an ion implanting process to an area of a semiconductor substrate in which the trench would be formed to cause lattice defects in the area before forming the trench, an etching speed of the area is increased in subsequent trench forming processes. As a result, it is possible to prevent micro trenches from being formed in edge portions of patterns and to suppress a micro loading effect to be generated depending upon pattern sizes.

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Chungcheongbuk-do, South Korea

Sang Wook Ryu