Samsung Electronics Co., Ltd.

Korea Advanced Institute of Science and Technology

Hyundai Electronics Industries Co. Ltd.

Lg Semicon Co., Ltd.

Sang-wook Han

Chul-ho Kim

Jae-young Kim

Shin-woong Kim

Jaehyuk Jang

Seong-deok Lee

Joo-Young Kang

Jae-hyuk Jang

Won-Hee Choe

Ho-Rang Jang

Ji-Woong Kwon

Young-Min Kim

Won-hee Choe

Joon-Hee Lee

Euisik Yoon

Jae-guyn Lim

Jung-Woo Kim

Byung-kwan Park

Hyun-Chul Song

Jae-Guyn Lim

A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.

Device including digital interface with mixture of synchronous and asynchronous communication, digital processing system including the same, and digital processing method performed by the same

Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.

Phase locked loop circuits, clock signal generators comprising digital-to-time convert circuits, operating methods thereof and wireless communication devices

In an operating method of a radio frequency integrated circuit (RFIC) including a transmission circuit and a reception circuit, the operating method includes receiving, from a modem, first information for setting transmission power of the transmission circuit or second information about a blocker which is a frequency signal unused by the RFIC, obtaining an allowable value of phase noise of a local oscillator included in the transmission circuit, using the first information, obtaining an allowable value of phase noise of a local oscillator included in the reception circuit, using the second information, determining a level of a driving voltage, using the obtained allowable values of the phase noises, and providing the driving voltage to the local oscillators.

Radio frequency integrated circuit including a local oscillator and operating method thereof

A crystal oscillator including a feedback circuit, and a reference clock generating circuit including the crystal oscillator. The crystal oscillator is configured to generate an oscillating signal based on a natural frequency of a crystal. The crystal oscillator may include: a current generating circuit connected to a first node having a first voltage and a second node having a second voltage, and configured to output a first current to the second node; a feedback circuit connected to the generating circuit via the first and second nodes and configured to adjust a level of the second voltage by controlling a level of the first voltage; and a crystal circuit connected to the second node and configured to generate the oscillating signal based on the second voltage.

Crystal oscillator and reference clock generator including same

A color filter array may include a plurality of pixels and control a pass wavelength band of the plurality of pixels using a dichroic filter that passes light of a specific wavelength range and blocks the rest of wavelengths. The pass wavelength band of the plurality of pixels may be adjusted according to a plurality of thicknesses of the dichroic filter. The dichroic filter may be formed by repeatedly forming a layer of titanium dioxide (TiO) and a layer of silicon dioxide (SiO).

Color filter array using dichroic filter

Disclosed are an image sensor and a local binning method in which binning is applied selectively. For example, binning is applied to pixels having low illumination and binning is not applied to non-low illumination pixels. Information on pixels having low illumination for a first image frame may be stored and used to perform binning with respect to areas of a second image frame corresponding to low illumination pixel areas determined with respect to the first image frame.

Image sensor and image processing method to acquire a high-sensitivity image

A technology of acquiring and processing light field data for images is provided. A light field data acquisition apparatus includes a modulator with an attenuation pattern to spatially modulate aD light field for an image, and a sensor to acquireD signals of the spatially modulatedD light field. By utilizing the attenuation pattern of the modulator, more spatial data may be acquired in a low angular frequency region than that acquired in a high angular frequency region.

Modulator, apparatus for obtaining light field data using modulator, and apparatus and method for processing light field data using modulator

The present invention provides a CMOS image sensor for broadening a dynamic range by controlling an integration time for each pixel to thereby obtain a high quality image with a low noise. The CMOS image sensor according to the present invention includes plural pixels, each for storing an integration time of a present frame, and control means for controlling the integration time of a next frame based on the stored integration time.

CMOS image sensor with wide dynamic range

The method and device for accessing a flash memory array receives a logical address for the flash memory array, which has been divided into a plurality of blocks. Each block of the flash memory array includes logical address to physical address conversion information for that block. After determining which block the received logical address corresponds, the conversion information for that block is obtained and stored. Memory access operations are then performed using the stored conversion information.

Flash memory array access method and device

A wear leveling system and method of a flash memory cell uses the amount of time required to perform an erasing operation on a sector of the flash memory to determine whether the memory cells in the sector have degraded to an unacceptable level. The actual time required to erase a sector of a flash memory array is compared to a reference erasing time required to erase a unit sector under the state of the worst allowable degradation. If the actual erasing time of a sector exceeds the reference erasing time, logical addresses corresponding to the sector are re-mapped to the physical addresses of a different sector. On the other hand, when the actual erasing time is shorter than or equal to the reference erasing time, a controller continues to use the unit sector.

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Seoul, South Korea

Sang-wook Han