Samsung Electronics Co., Ltd.

Sang-Woo Pae

Hyun-chul Sagong

Seung-Jin Choo

Hyun-Woo Lee

Hyun-Min Choi

Young-seok Jung

Dong-Uk Park

Hye-jin Kim

Phil-Jae Jeon

Jae-Hee Choi

Yong-sang Cho

Soon-Young Lee

Jong-wook Jeon

Hyun-Suk Chun

Da Rae Ahn

Da-Hye Min

Jin-Chul Park

Hye-Won Shim

Kyong-Taek Lee

June-Kyun Park

Sung-young Yoon

Min-jung Jin

Min-Jae Kwon

Seong-Won Jeong

Kwang-Won Choi

Hyun-Chul Sagong

A semiconductor device includes a substrate, a thermal conduction layer on the substrate, a first wire pattern on the thermal conduction layer, a first semiconductor pattern a second semiconductor pattern, and a gate electrode between the first semiconductor pattern and the second semiconductor pattern. The gate electrode surrounds a periphery of the first wire pattern. A concentration of impurity of the thermal conduction layer is different from that of the substrate. The first wire pattern includes a first end and a second end. The concentration of impurity contained in the first wire pattern is higher than that contained in the thermal conduction layer and that contained in the substrate. The first semiconductor pattern is in contact with the first end of the first wire pattern and the thermal conduction layer. The second semiconductor pattern is in contact with the second end of the first wire pattern.

Semiconductor device

A semiconductor package includes a package substrate, the package substrate including a conductive plate, an insulating plate on the conductive plate, the insulating plate including a mounting region and a peripheral region surrounding the mounting region, and at least one capillary channel in the peripheral region, a semiconductor chip on the mounting region of the insulating plate, and a molding member on the insulating plate to cover the semiconductor chip, a portion of the molding member being in the at least one capillary channel.

Package substrate and semiconductor package including the same

A clock switch device includes a control circuit and a tri-state buffer. The control circuit deactivates an output enable signal when a frequency of a clock signal varies and activates the output enable signal when the frequency of the clock signal is maintained without change. The tri-state buffer maintains an output electrode at a high impedance state when the output enable signal is deactivated and buffers the clock signal and outputs the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated.

Clock switch device and system-on-chip having the same

A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example and may identify a MOS transistor operating with its drain voltage higher than its gate voltage in the circuit. The design system and method may substitute a smaller transistor, having a high-k dielectric layer, for the original transistor in the circuit design.

Circuit design system and semiconductor circuit designed by using the system

A semiconductor device includes a substrate including a first active area extending in a first direction and a second active area extending in a second direction and connected to the first active area; first and second gate structures respectively crossing the first and second active areas; a first region in an area where the first and second active areas are connected to each other, the first region being on a first side of each of the first and second gate structures; a second region in the first active area on the other side of the first gate structure; and a third region formed in the second active area on the other side of the second gate structure.

Semiconductor device and method of manufacturing the same

A semiconductor test device includes an actuator holding a radiation source and adjusting a distance between the radiation source and a sample, and a controller controlling an operation of the actuator and calculating a soft error rate (SER) of the sample based on the distance between the radiation source and the sample. The controller calculates a first distance between the radiation source and the sample at which the SER of the sample becomes zero, and calculates a metal-to-dielectric ratio of the sample based on the first distance.

Semiconductor test device and method, and data analysis device

A one time programmable (OTP) memory device, a method of manufacturing the same, and an electronic device including the same, which lower a programming voltage to enhance programming efficiency, increase reliability of peripheral input/output (I/O) elements used for a design of the OTP memory device, and simplify the design, are provided. The OTP memory device includes a transistor including one of a first gate structure including a high-k dielectric layer, a rare earth element (RE) supply layer, and a second metal layer, a second gate structure including the high-k dielectric layer, a first metal layer, and the second metal layer, and a third gate structure including the high-k dielectric layer and the second metal layer.

One time programmable memory device, method of manufacturing the same, and electronic device including the same

A semiconductor device comprises a semiconductor chip which includes at least one gate structure on a substrate, the gate structure including a first region, a second region different from the first region, and a third region between the first and the second region, a first redistribution layer on a top surface of the semiconductor chip, the first redistribution layer configured to electrically connect a first electrode pad of the semiconductor chip to a first solder ball and overlap the first region of the gate structure, a second redistribution layer on the top surface of the semiconductor chip, the second redistribution layer configured to electrically connect a second electrode pad of the semiconductor chip to a second solder ball and overlap the second region of the gate structure such that the third region is exposed, and an insulating layer on the first redistribution layer and the second redistribution layer.

A semiconductor device includes a first fin pattern, which includes a first lower pattern and a first upper pattern stacked sequentially on a substrate, the first upper pattern including a first part and second parts respectively disposed on both sides of the first part, a gate electrode, which is formed on the first part to intersect the first fin pattern, and source/drain regions, which are formed on the second parts, respectively. A dopant concentration of the first upper pattern is higher than a dopant concentration of the first lower pattern and a dopant concentration of the substrate, and the dopant concentration of the first lower pattern is different from the dopant concentration of the substrate.

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Seongnam-si, South Korea

Sang-Woo Pae