Globalfoundries Inc.

Sang Woo Lim

Jinping Liu

Huang Liu

Shesh Mani Pandey

Yi Qi

Zhenyu Hu

Joseph Francis Shepard, Jr

Jianwei Peng

Hsien-Ching Lo

Matthew W Stoker

Pei Zhao

Alina Vinslava

Kyung-Bum Koo

A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3&#xd7; fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3&#xd7; fin pitch, a TS formed on the RSD, and an ILD formed over the TS.

Device with large EPI in FinFETs and method of manufacturing

Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

Single-curvature cavity for semiconductor epitaxy

Growing community of inventors

Ballston Spa, NY, United States of America

Sang Woo Lim