Samsung Electronics Co., Ltd.

Sang-won Park

Yohan Lee

Jiho Cho

Sang-wan Nam

Eunhyang Park

Won-taeck Jung

Heewon Son

Disclosed is a memory system including a memory device and a memory controller. The memory device includes a package of a first memory chip configured to receive input/output signals through first input/output pads and a second memory chip having second input/output pads connected to the first input/output pads by a mapping connection. The memory controller configured to provide the input/output signals to the memory device. The second memory chip is configured to receive input/output signals different from the input/output signals provided by the memory controller to the first memory chip due to the mapping connection. The first and second memory chips are configured to selectively ignore the input/output signals provided by the memory controller based on the mapping connection.

Memory device reducing i/o signal lines through i/o mapping connection and memory system including the same

A memory device includes a memory cell array, a reference generating circuit, a row decoding circuit that is connected to the memory cell array through word lines, a page buffer circuit that is connected to the memory cell array through bit lines, a data input/output circuit that is connected to the page buffer circuit through a data line, a buffer circuit, a control logic circuit that performs logic sequences, based on the internal clock signal and the internal power, and a test mode circuit. When the memory device enters a test mode, the test mode circuit disables a part of components of the reference generating circuit. In the test mode, the control logic circuit performs the logic sequences by using an external clock signal provided from an external device.

Memory device, operation method of memory device, and operation method of test device configured to test memory device

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SUWON-SI, South Korea

Sang-won Park