Samsung Electronics Co., Ltd.

Other

Yonsei University

Sungkyunkwan University

Sang-Won Park

Sang-won Shim

Sang-Wan Nam

Bongsoon Lim

Jung-Yun Yun

Kitae Park

Su-Chang Jeon

Dong-kyo Shim

Won Bo Shim

Won-Taeck Jung

Yonghyuk Choi

Hongsoo Jeon

Dongkyo Shim

Ji-Suk Kim

Donghun Kwak

Bong-Soon Lim

Bong Soon Lim

Ji Ho Cho

Ji Yeon Shin

Sang Gi Hong

Youn-Sun Kim

Hyoung-Ju Ji

Yohan Lee

Chiweon Yoon

Dongku Kang

Jinman Han

Dong-Hun Kwak

Jinhwan Kim

Ho-Jun Lee

Chung-Yong Lee

Su Chang Jeon

Jiho Cho

Han-Jun Lee

Eunhyang Park

Sang-Geun Lee

Wonbo Shim

Soo-Jung Kang

Bo-Il Shim

Hojoon Kim

Vo Thi Hai

Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n−1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n−1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.

Operation method of memory device and operation method of memory system including the same

A nonvolatile memory may include; a first memory cell array including a first selection transistor connected to a first string selection line, a second memory cell array including a second selection transistor connected to a second string selection line and spaced apart from the first string selection line by a first cutting line, and a peripheral circuit. The peripheral circuit may provide a first program voltage to the first selection transistor, provide a second program voltage to the second selection transistor different from the first program voltage, program the first selection transistor with a first threshold voltage in response to the first program voltage, and program the second selection transistor with a second threshold voltage level greater than the first threshold voltage in response to the second program voltage.

Nonvolatile memory and storage device including same

A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.

Three-dimensional semiconductor memory device

A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.

Erase method of non-volatile memory device

A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

Nonvolatile memory device and erase method thereof

A method for programming a non-volatile memory device is provided. The method comprises applying a program word line voltage with a voltage level changed stepwise to a selected word line connected to a plurality of memory cells, and applying a program bit line voltage to a first bit line of a plurality of bit lines connected to a plurality of first memory cells, while the program word line voltage is applied to the selected word line. The program bit line voltage transitions from a first voltage level to one of a program inhibit voltage level, a program voltage level, and a second voltage level. The first and second voltage levels are between the program inhibit voltage level and program voltage level.

Non-volatile memory device and method for programming the same

A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.

Nonvolatile memory device and storage device including nonvolatile memory device

A non-volatile memory device comprises a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region, and a control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines.

Non-volatile memory device

A semiconductor memory device includes a substrate, first memory cells that are connected to first word lines extending along a first direction and first bit lines extending along a second direction, over the substrate, first conductive materials that are connected to the first word lines and extend from the first word lines along a third direction perpendicular to the first direction and the second direction, second conductive materials that are connected to the first bit lines and extend along the first direction over the first bit lines, and third conductive materials that are connected to the second conductive materials and extend from the second conductive materials along the third direction.

Semiconductor memory device including parallel substrates in three dimensional structures

A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.

Nonvolatile memory device, vertical NAND flash memory device and SSD device including the same

A non-volatile memory device having a memory chip is provided. The memory chip having a memory cell array including a plurality of memory planes sharing a pad, the pad configured to communicate input and output signals. The memory chip also having a control circuit configured to monitor operations of the plurality of memory planes, and control an operation of at least one of the plurality of memory planes based on a result of the monitoring such that peak power intervals of the plurality of memory planes are at least partially distributed.

Non-volatile memory device including memory planes, and operating method thereof

A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.

Nonvolatile memory device and method of operation with a word line setup time based on two sequential read voltages

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Seoul, South Korea

Sang-Won Park