Samsung Electronics Co., Ltd.

Sang Won Hwang

Chan Kim

Jin Yub Lee

Dong Kyu Youn

Min Gun Park

Kyong Ae Kim

You Sang Lee

A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address.

Method and apparatus for performing multi-block access operation in nonvolatile memory device

A nonvolatile memory array includes first and second blocks of three-state memory cells therein. These first and second blocks are configured to operate individually as first and second blocks of physical memory cells, respectively, and collectively as an additional block of virtual memory cells. The first and second blocks of memory cells and the additional block of virtual memory cells may be read independently to provide a total of three blocks of read data.

Nonvolatile memory devices that support virtual page storage using odd-state memory cells

A non-volatile semiconductor memory device, including a memory array having a plurality of first bit line groups and a plurality of second bit line groups that are alternately arranged to be adjacent each other, a plurality of data lines, a plurality of first page buffers, a plurality of second page buffers, and a plurality of switches. Each of the first page buffers is electrically connected to a corresponding one of the first bit line groups and arranged on a first side of the memory array. The first page buffers transmit data to the data lines. Each of the second page buffers is electrically connected to a corresponding one of the second bit line groups and arranged on a second side of the memory array. Each of the switches enables data transmission between a corresponding one of the first page buffers and a corresponding one of the second page buffers.

Non-volatile semiconductor memory device using adjacent bit lines for data transmission and method of driving the same

A non-volatile semiconductor memory device may include a memory cell array and a controller coupled to the memory cell array. The memory cell array may include first and second memory cells coupled to respective first and second word lines. Each of the first and second memory cells may be configured to be programmed to one of a first, a second, or a third threshold voltage so that the first and second memory cells provide nine different threshold voltage combinations. The controller may be configured to provide a mapping of data of a set of three binary bits providing eight different data combinations to eight of the nine different threshold voltage combinations provided by the first and second memory cells. The controller may be further configured to write data of first, second, and third binary bits to the first and second memory cells by programming each of the first and second memory cells to a respective one of the first, second, or third threshold voltages using the mapping of data. Related methods are also discussed.

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Gyeonggi-do, South Korea

Sang Won Hwang