Samsung Electronics Co., Ltd.

Sang-Wan Nam

Won-Taeck Jung

Kitae Park

Chi-Weon Yoon

Junghoon Park

Donghyuk Chae

Chiweon Yoon

Chi Weon Yoon

Kang-Bin Lee

Dae-seok Byeon

Yoon-Hee Choi

Sang-Won Park

Jung-Yun Yun

Kyung-Hwa Kang

Jinwoo Park

Dong Hyuk Chae

Sang-won Shim

Sung-won Yun

Ji-Ho Cho

Won-Bo Shim

Bongsoon Lim

Jaeyong Jeong

Dae-Han Kim

Wandong Kim

Jae-Woo Park

Yang-Lo Ahn

Dong-Hun Kwak

Yonghyuk Choi

Doo-hyun Kim

Hongsoo Jeon

Kuihan Ko

Euihyun Cheon

Minsu Kim

Young-Ho Lim

Daeseok Byeon

Sunil Shim

Dong-Hyuk Chae

Sang-Soo Park

Bong-Soon Lim

Bong-Kil Jung

Jung-Soo Kim

Ji Ho Cho

Seongjin Kim

Won Bo Shim

Sun-Min Yun

Ji Yeon Shin

Won-Teack Jung

Sang Gi Hong

Byungjun Min

Jae-Hoon Lee

Jae-Yong Jeong

Hyun-Wook Wook Park

Hyunjung Kim

Yohan Lee

Tae-Hyun Kim

Dae-Seok Byeon

Byung-Gil Jeon

Seung-Keun Lee

Donghun Kwak

Jinman Han

Jong-Hoon Lee

Ho-Jun Lee

Jong Min Baek

Hyunggon Kim

Won-Tae Kim

Kihwan Choi

Eun-Suk Cho

Jun-Ho Seo

Jonghoon Park

Tae-hyun Kim

Se Hwan Park

Jae-Duk Yu

Jung-hoon Park

Jiho Cho

Wan-Dong Kim

Woo Chul Jung

Jin-Man Han

Woo-Pyo Jeong

Young-sun Min

Kyung-min Kang

Sung-whan Seo

Raeyoung Lee

Jung-ho Song

Sang-In Park

Sung-Bok Lee

Eunhyang Park

You-se Kim

Haneol Jang

Soyeong Gwak

Hyukje Kwon

Juseong Hwang

Min Ki Jeon

Younho Hong

Kee Ho Jung

Yong-Lae Kim

So-Yeong Gwak

Jae-Kyun Rhee

Yun-Ho Hong

Hae-Suk Shin

Disclosed is a nonvolatile memory device including a memory cell array including memory cells, bit lines and word lines connected with the memory cells, a common source line connected with the memory cells, a control logic circuit including a common source line noise control logic circuit and configured to generate voltages including a first voltage and a second voltage, a voltage selector configured to receive the voltages and configured to select at least one of the voltages, and a common source line driver configured to receive the at least one selected voltage and configured to control a voltage of the common source line, and the common source line noise control logic circuit is configured to control the voltage selector based on program information so as to select the at least one of the voltages.

Nonvolatile memory device and storage device including nonvolatile memory device including a voltage selector

A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.

3D flash memory device having dummy word lines and dummy word line voltage generators

Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n−1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n−1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.

Operation method of memory device and operation method of memory system including the same

At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where 'k' is 2 or a natural number greater than 2.

Address scheduling methods for non-volatile memory devices with three- dimensional memory cell arrays

A nonvolatile memory device includes: a memory cell array including three or more planes; a first clock generator generating a first clock signal having a first period; a second clock generator generating a second clock signal having a second period that varies with the temperature; a plurality of clock switching controllers outputting one of the first and second clock signals as a reference clock signal; a control logic including a plurality of bitline shutoff generators, which output a plurality of bitline shutoff signals based on the reference clock signal; and a plurality of page buffers connecting bitlines of the planes and data latch nodes in accordance with the bitline shutoff signals.

Nonvolatile memory device with multiple clocks

Disclosed is a memory device includes a memory block that is connected with a plurality of wordlines, a voltage generating circuit configured to output a first non-selection voltage through a plurality of driving lines, and an address decoding circuit configured to connect the plurality of driving lines with unselected wordlines of the plurality of wordlines. During a wordline setup period for the plurality of wordlines, the voltage generating circuit floats first driving lines corresponding to first unselected wordlines of the unselected wordlines from among the plurality of driving lines when the first unselected wordlines reach a first target level, and floats second driving lines corresponding to second unselected wordlines of the unselected wordlines from among the plurality of driving lines when the second unselected wordlines reach a second target level different from the first target level.

Memory device and operation method thereof

A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.

Non-volatile memory device and memory system including the same and program method thereof

A nonvolatile memory device including a memory cell array, a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array, a second voltage generator configured to generate a bit line operating voltage of the memory cell array, and a temperature unit configured to determine, from a temperature range table, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of the first or second voltage generator based on a selection signal mapped to the determined temperature range.

Non-volatile memory device implementing temperature compensation features

A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.

Three-dimensional semiconductor memory device

A nonvolatile memory device includes a memory block including a first structure formed on a substrate and a second structure formed on the first structure. An erase method of the nonvolatile memory device includes applying a word line erase voltage to first normal word lines of the first structure and second normal word lines of the second structure, and applying a junction word line erase voltage smaller than the word line erase voltage to at least one of a first junction word line of the first structure and a second junction word line of the second structure. The first junction word line is a word line adjacent to the second structure from among word lines of the first structure, and the second junction word line is a word line adjacent to the first structure from among word lines of the second structure.

Erase method of nonvolatile memory device, and operation method of storage device

Address scheduling methods for non-volatile memory devices with three-dimensional memory cell arrays

An operation method of a nonvolatile memory device includes receiving a read command and an address, increasing a voltage applied to an unselected word line from an off voltage to a read pass voltage during a setup phase in response to the read command, increasing a voltage applied to an unselected string selection line from the off voltage to a pre-pulse voltage during a first setup phase of the setup phase, increasing a voltage applied to an unselected ground selection line from the off voltage to the pre-pulse voltage during the first setup phase, applying a read voltage to a selected word line to read data corresponding to the address, during a sensing phase following the setup phase, and outputting the read data through data lines after the sensing phase. During the setup phase, a slope of the voltage applied to the unselected word line is varied.

Operation method of nonvolatile memory device

A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

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Hwaseong-si, South Korea

Sang-Wan Nam