Silicon Storage Technology, Inc.

Crossbar, Inc.

Sang Thanh Nguyen

Hung Quoc Nguyen

Hieu Van Tran

Anh Ly

Hagop A Nazarian

Loc Bao Hoang

Vishal Sarin

Thuan Vu

Nasrin Jaffari

Sung Hyun Jo

Sheng-Hsiung Hsueh

Steve Choi

Wingfu AAron Lau

Zhi Li

Tanmay Kumar

Tianhong Yan

William Saiki

Hung O Nguyen

Yuniarto Widjaja

Alexander Kotov

Tam Minh Nguyen

Lin Shih Liu

Tho Ngoc Dang

Cung Vu

Jeremy Guy

Phil Klotzkin

Mehdi Asnaashari

Dzung Huu Nguyen

Nianglamching Hangzo

John D Nguyen

Thuc Tran Bui

Elbert Lin

Tam Huu Tran

Layne Armijo

Sandie Tran

Niang Hangzo

A field programmable gate array (FPGA) utilizing resistive switching memory technology is described. The FPGA can comprise a switching block interconnect having a set of signal input lines and a set of signal output lines. Respective intersections of the signal input lines and signal output lines can have two resistive switching memory cells, a current differential latch, and a switching transistor (also referred to as a pass gate transistor) arranged in a circuit. Resistance states of the resistive switching memory cells can be programmed to control an output voltage state of the current differential latch. The output voltage state is latched into the current differential latch which can drive a gate of the switching transistor to activate or deactivate the switching transistor, which in turn activates or deactivates an intersection of the FPGA.

Configuration bit using RRAM

Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip

An herbal composition includes a plurality of herbal components designed to work harmoniously together to alleviate pain and reduce inflammation of the oral mucosa. Such pain and inflammation may be associated with, for example, recurrent aphthous stomatitis. The formulation can include ginger, cayenne, cloves, cinnamon, turmeric, and annatto. The herbal composition may be formulated as a candy or gum, for example, to provide effective delivery to the oral mucosa.

Formulation and delivery systems for herbal compositions for the treatment of canker sores (recurrent aphthous stomatitis) and related conditions

A method for facilitating erase or program operations on two-terminal memory devices includes substantially simultaneously initiating erase cycle or program cycle for two-terminal memory devices from a first plurality of two-terminal memory devices, monitoring erase detect or program detect conditions for each of the two-terminal memory devices, and before detecting erase detect or program detect conditions for all of the two-terminal memory devices, the method includes detecting an erase detect or a program detect condition for the first two-terminal memory device from the first plurality of two-terminal memory devices, and initiating an erase cycle or a program for a second two-terminal memory device for a second plurality of two-terminal memory devices, in response to detecting the erase detect or program detect condition for the first two-terminal memory device.

Methods and apparatus for facilitated program and erase of two-terminal memory devices

A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state, e.g., to a defined higher resistance state or a defined lower resistance state. Other, techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that cause the state change and can do so by comparing the magnitudes or values of two particular current parameters.

State change detection for two-terminal memory

Two-terminal memory can be formed into a memory array that contains many discrete memory cells in a physical and a logical arrangement. Where each memory cell is isolated from surrounding circuitry by a single transistor, the resulting array is referred to as a 1T1R memory array. In contrast, where a group of memory cells are isolated from surrounding circuitry by a single transistor, the result is a 1TnR memory array. Because memory cells of a group are not isolated among themselves in the 1TnR case, bit disturb effects are theoretically possible when operating on a single memory cell. Read operations are disclosed for two-terminal memory devices configured to mitigate bit disturb effects, despite a lack of isolation transistors among memory cells of an array. Disclosed operations can facilitate reduced bit disturb effects even for high density two-terminal memory cell arrays.

Read operation with data latch and signal termination for 1TNR memory array

State change detection for two-terminal memory utilizing current mirroring circuitry

A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, coupling a second electrode of the first resistive element, and a first electrode of the second resistive element to a first terminal of a first transistor element, coupling a second terminal of the first transistor element to a first terminal of a latch, coupling a second terminal of the latch to a gate of a second transistor element, and coupling a gate of the first transistor element to a latch program signal.

Field programmable gate array utilizing two-terminal non-volatile memory

A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, applying a first programming voltage to a shared node of a second electrode of the first resistive element, a first electrode of the second resistive element, and to a gate of a transistor element, and changing a resistance state of the first resistive element to a low resistance state while maintaining a resistance state of the second resistive element, when a voltage difference between the first programming voltage at the second terminal and the first input voltage at the first terminal exceeds a programming voltage associated with the first resistive element.

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Fremont, CA, United States of America

Sang Thanh Nguyen