Samsung Electronics Co., Ltd.

Sang-suk Kang

Jong-hyoung Lim

Jong-hyun Choi

Jung-Hyun Nam

Kyu-Nam Lim

An apparatus and a method are disclosed for package level burn-in test circuit in semiconductor devices. The apparatus includes a package burn-in register, a test voltage generator for the package level burn-in test, a burn-in master signal generator, and a burn-in test circuit. The package burn-in register stores a package burn-in set-order from the outside and generates a package burn-in set-signal. The test voltage generator generates burn-in test voltages in response to the package burn-in set-signal and to address signals through first address terminals from the outside. The burn-in master signal generator generates a burn-in master signal by combining and receiving the second address signal form first address terminals, a wafer burn-in enable signal from a control signal input terminal, and the package burn-in set-signal. After receiving the burn-in master signal, multiple address signals from multiple third address terminals, and the test voltages for the package level burn-in test, the burn-in test circuit performs a package level burn-in test.

Apparatus and method for package level burn-in test in semiconductor device

Integrated circuit devices having improved test capabilities may include a mode selection circuit that generates a mode signal that designates an operational mode based on the magnitude of a mode control signal when a power supply signal transitions from a first state to a second state. A preferred embodiment of the mode selection circuit generates a mode signal that designates a first mode of the integrated circuit device when the power supply signal transitions from a first state to a second state while a magnitude of the mode control signal exceeds a potential threshold. Moreover, the mode selection circuit may also prevent subsequent changes in the magnitude of the mode control signal from disabling the first mode. The mode signal may be generated without the need for additional dummy pads and/or input pins, which may necessitate an increase in chip size and/or more complex test equipment to test an integrated circuit device.

Integrated circuit devices having mode selection circuits that generate a mode signal based on the magnitude of a mode control signal when a power supply signal transitions from a first state to a second state

A dual-purpose transmission circuit capable of receiving two or more signals or voltages, or a signal and a voltage, using one input pad, and an input method using the circuit. The dual-purpose transmission circuit includes an internal signal line for transmitting a signal to the inside of the semiconductor device, an internal voltage line for transmitting a voltage to the inside of the semiconductor device, a first transmission portion for connecting the internal signal line to the outside of the semiconductor device in response to a control signal, in a signal input mode, and a second transmission portion for connecting the internal voltage line to the outside of the semiconductor device in response to the control signal, in a voltage input mode.

Signal routing circuits having selective high impedance and low

Integrated circuit devices include preferred mode selection circuits therein which generate a signal that designates a first mode of the integrated circuit device when a potential of a first control signal is within a first range and a potential of a power supply signal (e.g., Vcc) is within a second range at the same time. The mode selection circuit also prevents changes in the potential of the first control signal from disabling the first mode when the potential of the power supply signal is not within the second range. When the integrated circuit device is a memory device, the first control signal may be a row or column address signal (Ai), for example. The mode selection circuit may comprise a level shifter which generates a downward level shifted version of the address signal. The mode selection circuit generates a signal that designates a first mode of the memory device when a potential of the address signal exceeds a first threshold (e.g., 5 volts) and a potential of the power supply signal (Vcc) is below a second threshold at the same time. The mode selection circuit also prevents changes in the potential of the address signal (Ai) from disabling the first mode so long as a potential of the power supply signal (Vcc) exceeds the second threshold.

Growing community of inventors

Kyunggi-do, South Korea

Sang-suk Kang