Samsung Electronics Co., Ltd.

Sang-su Kim

Hwa-sung Rhee

Nae-in Lee

Geum-jong Bae

Tae-hee Choe

Kyung-wook Lee

Geum-Jong Bae

Jung-il Lee

Ki-Chul Kim

Ki-chul Kim

Sung-Ho Kim

Jin-Hee Kim

In-Wook Cho

Kwang-wook Koh

Young-ki Ha

CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A SiGelayer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The SiGelayer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the SiGelayer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the SiGelayer varies from the peak level where 0.2&#x3c;x&#x3c;0.4 to a level where x=0 at the first junction. The SiGelayer also has a retrograded arsenic doping profile therein relative to the surface. This retrograded profile may result in the SiGelayer having a greater concentration of first conductivity type dopants therein relative to the concentration of first conductivity type dopants in a channel region within the unstrained silicon active layer. The total amount of dopants in the channel region and underlying SiGelayer can also be carefully controlled to achieve a desired threshold voltage.

CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same

Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

Byte-operational nonvolatile semiconductor memory device

Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein

CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same

A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed by patterning the poly-SiGe layer. It is possible to form a gate whose bottom is shorter than its top defined by photolithography by taking advantage of the variation of etching characteristics with Ge density when patterning. Accordingly, the gate is compact enough for a short channel device and gate resistance can be reduced.

Semiconductor device having gate with negative slope and method for manufacturing the same

Provided is a method for fabricating a semiconductor device. According to the method, an insolating layer which defines an active region on a semiconductor substrate is formed and a gate is formed on the active region of the semiconductor substrate. A first spacer layer which covers the gate and is extended to cover the isolating layer is formed as a first insulating material. A second spacer layer is formed on the first spacer layer as a second insulating material. A second spacer which remains on the sidewalls of the gate by removing some portions of the second spacer layer is formed. A first spacer by a portion of the first spacer layer, which is protected by the second spacer by partially etching the exposed portions of the first spacer layer using the second spacer as a mask so as to reduce the thickness of the first spacer layer, and a protection layer, which protects the insulating layer by remaining the portion of the first spacer of which thickness is reduced, are formed. The second spacer is selectively removed and a gate spacer of the first spacer is formed by removing the remaining protection layer.

Method for fabricating semiconductor device including gate spacer

A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is formed on a PMOS region of a semiconductor substrate, and a second gate pattern of polysilicon is selectively grown from an underlying layer. Although the first gate pattern on the PMOS region is formed of poly-SiGe, the characteristics of the second gate pattern on the NMOS region do not deteriorate, thereby increasing the overall characteristics of a CMOS transistor.

CMOS gate electrode using selective growth and a fabrication method thereof

CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si Ge layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si Ge layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peal Ge concentration level is greater than x&equals;0.15 and the concentration of Ge in the Si Ge layer varies from the peak level to a level less than about x&equals;0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si Ge layer varies from the peak level where 0.2<x<0.4 to a level where x&equals;0 at the first junction. The Si Ge layer also has a retrograded arsenic doping profile therein relative to the surface.

CMOS integrated circuit devices and substrates having unstrained silicon active layers

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Kyungki-do, South Korea

Sang-su Kim