Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Ymc Co., Ltd.

Sang-Su Kim

Geum-Jong Bae

Hwa-sung Rhee

Nae-in Lee

In-Wook Cho

Tae-hee Choe

Ki-chul Kim

Jung-Gil Yang

Jin-Hee Kim

Geum-jong Bae

Jae-Hwan Lee

Tae-yong Kwon

Sung-Ho Kim

Tae-Jong Lee

Seung-mo Ha

Jung-han Lee

Hwan-Wook Choi

Byoung-jin Lee

Shigenobu Maeda

Jung-dal Choi

Jae-Hoo Park

Sung-Gi Hur

Myeong-Cheol Kim

Sung-Hwan Kim

Sung-Taeg Kang

Byoung-Seong Jeong

Sung-Woo Lee

Young-Gun Ko

Doo-youl Lee

Jeong-Hwan Yang

Kwang-Wook Koh

Jin-hee Kim

Je-Hyun Song

Byou-ree Lim

Chang-Jae Yang

Kwang-wook Koh

Jung-Il Lee

Tae-Yong Kwon

Tae-Hun Lee

Sung-Won Yang

Tae-Hyung Kim

Cheol Kyu Kim

Gi-Gwan Park

Jong-Won Hong

Tae-hyung Kim

Yong-Suk Tak

Jung-il Lee

Yong-Ho Jeon

Seok-Hoon Kim

Seung-Min Song

Sun-Ghil Lee

Ki-Chul Kim

Dong-kyu Lee

Myung-geun Song

Jin-yeong Joe

Kyung Il Park

Sun-wook Kim

Yun-Ho Chang

Chung-Geun Koh

Kazuyuki Fujihara

Soo-jin Jeong

Byou-Ree Lim

Xingui Zhang

Xin-Gui Zhang

Keun-Ik Jeon

Youn-Yong Lee

Dong-Min Yoo

Tae-Woo Noh

Seung-Joo Hyun

Eun-Gook Sung

Jung-II Lee

A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

Semiconductor devices

FinFET semiconductor device with a dummy gate, first gate spacer and second gate spacer

A semiconductor device includes: a fin-type active area extending in a first direction protruding from a substrate; a plurality of nanosheet stacked structures; a blocking film covering a part of the upper surface and one sidewall of each of a pair of nanosheet stacked structures adjacent to both sides of the fin-type active area among the plurality of nanosheet stacked structures; a gate electrode extending in a second direction intersecting the first direction on the fin-type active area, the gate electrode including a real gate electrode surrounding the plurality of nanosheets and a dummy gate electrode disposed on the blocking film; and a gate dielectric layer between the real gate electrode and the plurality of nanosheets and between the dummy gate electrode and the blocking film.

Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

Methods of fabricating semiconductor devices

A multi-functional apparatus for testing and etching a substrate capable of increasing spatial efficiency and manufacturing efficiency by performing testing and etching operations in a same chamber body and a substrate processing apparatus including the same, the multi-functional apparatus including a chamber body having an entrance into which the substrate is injected in one of its sides and an exit from which the substrate is ejected in another one of its sides; a transfer unit disposed inside of the chamber body and for transferring the injected substrate in a direction from the entrance to the exit; a laser etching unit disposed on an upper portion of the transfer unit and for etching a part of the substrate disposed on the transfer unit; and a testing unit for testing the substrate disposed on the transfer unit.

Multi-functional apparatus for testing and etching substrate and substrate processing apparatus including the same

Semiconductor devices and methods of manufacturing the same

A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.

Semiconductor device and method for fabricating the same

A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.

Semiconductor device including nanowire transistor

Example embodiments relate to a metal-oxide semiconductor field effect transistor (MOSFET) of a high performance operating with a necessary threshold voltage while including a channel region formed based on a group III-V compound, and a method of manufacturing the MOSFET. The MOSFET includes a substrate, a semiconductor layer including a group III-V compound on the substrate, and a gate structure disposed on the semiconductor layer, and including a gate electrode formed based on metal and undergone an ion implantation process.

Metal-oxide semiconductor field effect transistor, method of fabricating the same, and semiconductor apparatus including the same

A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode and between first source and drain regions. The second transistor includes a second nanowire extending through a second gate electrode and between a second source and drain regions. The first nanowire has a first size in a first direction and a second size in a second direction, and the second nanowire has a second size in the first direction and substantially the second size in the second direction. The first nanowire has a first on current and the second nanowire has a second on current. The on current of the first nanowire may be substantially equal to the on current of the second nanowire based on a difference between the sizes of the first and second nanowires. In another arrangement, the on currents may be different.

Methods of manufacturing semiconductor devices having a nanowire channel structure

A semiconductor device includes a substrate, a compound semiconductor layer, and first and second semiconductor patterns. The substrate includes first and second regions. The first semiconductor pattern is on the compound semiconductor layer of the first region and includes an element semiconductor. The second semiconductor pattern is on the compound semiconductor layer of the second region and includes a Group III-V semiconductor material.

Growing community of inventors

Yongin-si, South Korea

Sang-Su Kim