Samsung Electronics Co., Ltd.

Hynix Semiconductor Inc.

Skhynix Inc.

Hyundai Electronics Industries Co. Ltd.

Sang-Soo Park

Jae-Yong Jeong

Il Han Park

Sang-Wan Nam

Byung Soo Kim

Jong-Hoon Lee

Dongkyo Shim

Dong-kyo Shim

Jae-Yun Lee

Tae-Hyeok Lee

Chan-Bae Kim

Joon Soo Kwon

Kitae Park

Jae-hyun Kim

Tae-Hyun Kim

Donghun Kwak

Ji-sang Lee

Bong-Soon Lim

Jaeyong Jeong

Jong-chul Park

Ho-Chul Hwang

Kang-Bin Lee

Yongsung Cho

Moosung Kim

Doo-hyun Kim

Wandong Kim

Ky-Hyun Han

Se Hwan Park

June-Hong Park

Won-Bo Shim

Ji-Suk Kim

Yoon Jin Kim

Jung-Taik Cheong

Wan-Dong Kim

Su-Yong Kim

Jun-Soo Lee

Jaewoo Im

Byeong-Jun Kim

Taekyun Kang

Joon-Soo Kwon

Hyuk-Jun Yoo

Na-Young Choi

Chang-Heon Park

Doo-Ho Cho

Dong-Ryeol Lee

Hyun-Young Yoo

Ki Ho Chung

Su-Bum Shin

Seung-In Shin

Gi-Hyeon Kim

A method for fabricating a semiconductor device includes: forming a first conductive structure over a substrate; forming a multi-layer spacer including a non-conformal sacrificial spacer on both sidewalls of the first conductive structure; forming a second conductive structure adjacent to the first conductive structure with the multi-layer spacer therebetween; forming an air gap by removing the non-conformal sacrificial spacer; forming a capping layer covering the second conductive structure and the air gap; forming an opening that exposes a top surface of the second conductive structure by etching the capping layer; and forming a conductive pad coupled to the second conductive structure in the opening.

Semiconductor device with air gap and method for fabricating the same

A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.

Memory device including a circuit for detecting word line defect and operating method thereof

To operate a memory device including a plurality of NAND strings, an unselected NAND string among a plurality of NAND strings is floated when a voltage of a selected word line is increased such that a channel voltage of the unselected NAND string is boosted. The channel voltage of the unselected NAND string may be discharged when the voltage of the selected word line is decreased. The load when the voltage of the selected word line increases may be reduced by floating the unselected NAND string to boost the channel voltage of the unselected NAND string together with the increase of the voltage of the selected word line. The load when the voltage of the selected word line is decreased may be reduced by discharging the boosted channel voltage of the unselected NAND string when the voltage of the selected word line is decreased. Through such reduction of the load of the selected word line, a voltage setup time may be reduced and an operation speed of the memory device may be enhanced.

Memory device including NAND strings and method of operating the same

A flash memory controller for a flash memory system includes an ECC circuit that receives first page data and second page data read from the flash memory, and respectively counts a first number of fail bits in the first page data and a second number of fail bits in the second page data, an abnormal wordline detector configured to compare the first number of fail bits and second number of fail bits to derive a fail bit change rate between the first page data and the second page data, and generate an abnormal wordline detection signal in response to the fail bit change rate, and a control unit that controls operation of the flash memory in response to the abnormal wordline detection signal.

Flash memory system having abnormal wordline detector and abnormal wordline detection method

A memory device can include: a memory cell array including a memory cell and a word line that is connected to the memory cell; a clock generator configured to generate a first pumping clock signal from a system clock signal; a charge pump configured to provide a pumping voltage signal using a power supply voltage and the first pumping clock signal; a compensation circuit configured to compensate for variations in a first reference clock signal in accordance with variations in the power supply voltage, and provide a compensated first reference clock signal; and a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing the first pumping clock signal and the compensated first reference clock signal while the pumping voltage signal is provided to the word line.

Memory devices including a word line defect detection circuit

A nonvolatile memory device performs a method which includes: causing a ready/busy signal pin of the nonvolatile memory device to indicate that the nonvolatile memory device is in a precharge busy state wherein the nonvolatile memory device is not available to perform memory access operations for its nonvolatile memory cells; applying one or more word line precharge voltages to one or more selected word lines among a plurality of word lines of the nonvolatile memory device to precharge the selected word lines; and, after at least a portion of the precharge operation, causing the ready/busy signal pin to transition from indicating the precharge busy state, to indicating that the nonvolatile memory device is in a ready state wherein the nonvolatile memory device is available to perform memory access operations for its nonvolatile memory cells.

Nonvolatile memory device, operating method of nonvolatile memory device, and storage device including nonvolatile memory device

A nonvolatile memory device includes a cell array comprising memory cells; a voltage generator that provides a program or verification voltage to a word line of memory cells selected from the memory cells; a page buffer that transfers write data to be programmed in the selected memory cells through bit lines and to sense whether the selected memory cells are programmed to target states, based on the verification voltage; and a control logic that controls the voltage generator such that the program voltage and the verification voltage are provided to the word line in units of multiple loops during a program operation, the control logic including a loop status circuit that detects values of state pass loops associated with the target states from a sensing result of the page buffer and determines whether the program operation is successful, based on the values of the state pass loops.

Nonvolatile memory device generating loop status information, storage device including the same, and operating method thereof

A nonvolatile memory device includes a memory cell array that stores data, and control logic. The control logic is configured to control a read operation, a program operation, or an erase operation on the data. The control logic is configured to detect a first power noise based on one of voltage sources to be provided to the memory cell array and a first reference voltage and detect a second power noise based on the one voltage source of the voltage sources and each of the first reference voltage and a second reference voltage. The control logic is configured to determine whether to perform at least one of an operation period of the read operation, an operation period of the program operation, or an operation period of the erase operation, based on whether at least one of the first and second power noises is detected.

Nonvolatile memory device detecting power noise and operating method thereof

Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a cell array including a plurality of memory cells, a page buffer including a plurality of latch sets, and a control logic. The page buffer is connected to the cell array through bit lines. The latch sets respectively are configured to sense data from selected memory cells among the memory cells through the bit lines. The latch sets respectively are configured to perform a plurality of read operations to determine one data state. The latch sets are respectively configured to store results of the read operations. The control logic configured to control the page buffer such that the latch sets sequentially and respectively store the results of the read operations, to compare data stored in the latch sets with each other, and to select one latch set among the latch sets based on the comparison result.

Nonvolatile memory device and read method thereof

A memory device is provided as follows. A memory cell array includes a plurality of memory cells, and the plurality of memory cells are divided into a first memory group and a second memory group. A first page buffer group is coupled to the first memory group and includes a plurality of first page buffers. A second page buffer group is coupled to the second memory group and includes a plurality of second page buffers. The first page buffer group performs a first data processing operation on data stored in the first page buffer group and stores a result of the first data processing operation. The second page buffer group performs a second data processing operation on data stored in the second page buffer group and stores a result of the second data processing operation. The first and second data processing operations are performed at substantially the same.

Memory device and method of operating the same

A nonvolatile memory device with a memory cell array including a plurality of memory cells coupled to first through M-th wordlines and first through N-th bitlines (M&#x3e;2, N&#x3e;2), and a page buffer circuit including first through N-th page buffers that are coupled to the first through N-th bitlines, respectively, and generate first through N-th output data, respectively. A K-th page buffer includes first through L-th latches which generate read data by sampling a voltage of a K-th output line, which is discharged through a K-th bitline, at different sampling timings after a read voltage is applied to a P-th wordline (K&#x2264;N, L&#x3e;1, P&#x2264;M). The K-th page buffer outputs the first output data if an error in the read data of the first latch is correctable.

Nonvolatile memory device and a method of operating the same

A method of operating a nonvolatile memory device that includes a three-dimensional (3D) memory cell array is provided as follows. A first read operation is performed on first memory cells connected to a first word line by using a first read voltage level. A read retry operation is, if the first read operation fails, performed on the first memory cells so that a read retry voltage level is set to a second read voltage level. A read offset table is determined based on a difference between the first read voltage level and the second read voltage level. The read offset table stores a plurality of read voltage offsets. A second read operation is performed on second memory cells connected to a second word line by using a third read voltage level determined using the read offset table.

Nonvolatile memory device, memory system, method of operating nonvolatile memory device, and method of operating memory system

A method of erasing a non-volatile memory device which includes a plurality of NAND strings is provided as follows. A first voltage is applied to each of word lines for a corresponding effective erasing execution time. An erase operation is performed on memory cells connected to each of the word lines for the corresponding effective erasing execution time. A second voltage is applied to each of at least some word lines among the word lines for a corresponding erasing-prohibited time after the corresponding effective erasing execution time elapses. A sum of the corresponding effective erasing execution time and the corresponding erasing-prohibited time for each of the at least some word lines is substantially equal to an erasure interval during which an erase operation is performed using the first voltage and the second voltage higher than the first voltage. The word lines are stacked on a substrate.

Memory device, memory system, method of operating the memory device, and method of operating the memory system

The present disclosure provides an electronic device and method for playing image data. The method for playing back image data in an electronic device includes storing an audiovisual (A/V) data for a predetermined period of time in a memory of the electronic device. The electronic device plays back the A/V data, wherein upon playing back, by the electronic device, the A/V data comprises analyzing an audio signal of the A/V data dynamically to select one of a plurality of sound effects based on the analyzed audio signal. The A/V data is played back by applying the selected sound effect to at least a part of the A/V signal.

Electronic device and method for playing back image data

Growing community of inventors

Hwaseong-si, South Korea

Sang-Soo Park