Skhynix Inc.

Dongbu Hitek Co., Ltd.

Korea Advanced Institute of Science and Technology

Sang Sik Kim

Sang Chul Lee

Dae Sung Kim

Jae Yoon Lee

Jaekyun Moon

Jun Seok Park

Chung Un Na

Joong Seob Yang

Ho Yeon Lee

Yong Rok Kim

Seok Hwan Choi

Hyo Ju Park

Seung Ho Chang

Sung Kwan Jung

Yong Chul Shin

Jaehyeong No

Joon Yeong Park

A memory system includes a nonvolatile memory device and a controller. The nonvolatile memory device includes a memory block including a plurality of memory cells, a first memory region of memory cells coupled to a first word line and a second memory region of memory cells coupled to a second word line. The controller performs a single level cell (SLC) program operation on the second memory region and perform a fine program operation on the first memory region after a completion of the SLC program operation on the second memory region.

Memory system and operating method thereof for performing urgent fine program operation

A memory system includes a memory device including a plane including a plurality of memory blocks for storing multi-bit data; and a controller configured to detect, when a problem-causing operation is performed on a first memory block among the memory blocks, remaining memory blocks, except the first memory block, in the plane as being in a problem occurrence candidate group, search for a table, when a read command for a second memory block of the problem occurrence candidate group is received, for a read voltage application order corresponding to the second memory block, and control the memory device to perform a read operation on the second memory block by sequentially applying a plurality of read voltages according to the searched read voltage application order, wherein the problem-causing operation is a program operation or an erase operation.

Memory system and operating method thereof

A memory controller configured to control a memory device including memory cells includes an input/output buffer configured to store input data provided from a host; a data converter configured to generate program data obtained by converting the input data such that the number of specific data patterns among data patterns to be stored in the memory cells is changed; and an operation controller configured to provide the program data to the memory device. The program data is generated by selectively inverting a plurality of pieces of logical page data included in the input data.

Storage device and method of operating the same

Provided herein is a semiconductor memory device exhibiting improved operating speed and a method of operating the semiconductor memory device. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a read operation on the memory cell array. The control logic may control an operation of the peripheral circuit. The control logic may control the peripheral circuit to perform a repair column masking operation on a selected memory block of the plurality of memory blocks, perform a first test operation on first drain select transistors included in the selected memory block, perform the first test operation on second drain select transistors different from the first drain select transistors while a result of the repair column masking operation remains.

Semiconductor memory device and method of operating the same

A system and method for transferring content among multiple devices are disclosed. Herein, the system for transferring content may include a coupling controller configured to identify a user equipment in accordance with a content transfer request and to perform coupling with the identified user equipment, and a content transfer unit configured to transmit content to the user equipment or to receive content from the user equipment, when coupling is completed.

System and method for transferring content among devices

A semiconductor device includes: memory blocks including main data storage units and cycling information storage units; a circuit group that performs a wear leveling operation on the memory blocks; and a control circuit that sets a threshold value based on the cycling information, and controls the circuit group so that the wear leveling operation is performed based on the set threshold value.

Semiconductor device and operating method thereof

A data storage device may include: a nonvolatile memory device including first and second memory cells adjacent to each other; and a controller suitable for performing a distribution adjusting operation for adjusting a threshold voltage of the second memory cell based on whether a read operation on the first memory cell fails.

Data storage device and operating method thereof

A method for estimating channel characteristics of a nonvolatile memory device including a plurality of memory cells includes the steps of: calculating first threshold voltage distributions of the memory cells programmed according to input data, based on the input data and a physical structure of the memory cells; calculating second threshold voltage distributions of the memory cells, based on output data and the physical structure of the memory cells; and analyzing the relation between the first and second threshold voltage distributions, using a mask.

Method for estimating channel characteristics of nonvolatile memory device

A Complementary Metal Oxide Semiconductor (CMOS) image sensor and methods for fabricating the same. In one example embodiment of the invention, a method for manufacturing a Complementary Metal Oxide Semiconductor (CMOS) image sensor includes several acts. First, a metal pad is formed over a semiconductor substrate. Next, a protection film is formed over the semiconductor substrate and the metal pad. Then, the protection film is selectively removed to expose a surface of the metal pad. Next, a first planarization film is formed over the protection film. Then, a color filter layer is formed over the first planarization film. Next, a second planarization layer is formed over the color filter layer. Then, a first material layer is formed over the second planarization layer. Next, a second material layer is formed over the first material layer. Then, a micro lens is formed out of the first and second material layers.

CMOS image sensor and method for fabricating the same

Embodiments relate to a method of manufacturing an image sensor. According to embodiments, the method may include preparing a semiconductor substrate formed with a plurality of photodiodes, forming an interlayer dielectric layer on the semiconductor substrate, forming a color filter layer on the interlayer dielectric layer, forming a planar layer on the color filter layer, and forming micro-lenses coated with fat-soluble polymer on the planar layer. Since the micro-lens is uniformly formed due to the fat-soluble polymer coated on the micro-lens, the photo-sensitivity and color reproduction of the image sensor are improved, resulting in the high-quality image sensor.

Image sensor

Embodiments relate to an image sensor and a method of manufacturing an image sensor. In embodiments, the method may include preparing a semiconductor substrate formed with a plurality of photodiodes, forming an interlayer dielectric layer on the semiconductor substrate, forming a color filter layer on the interlayer dielectric layer, forming a planar layer on the color filter layer, and forming micro-lenses on the planar layer by using heat transfer liquid. Heat is uniformly applied to the micro-lens because the micro-lens is immersed in the heat transfer liquid having the high temperature, so the micro-lenses are prevented from being bonded to each other. Since a curvature surface of the micro-lens may be uniformly formed, the photo-sensitivity and color reproduction of the image sensor may be improved, which may result in a high-quality image sensor.

Growing community of inventors

Gyeonggi-do, South Korea

Sang Sik Kim