Hynix Semiconductor Inc.

Skhynix Inc.

Hynis Semiconductor Inc.

Sang-Sic Yoon

Kyung-Hoon Kim

Beom-Ju Shin

Bo-Kyeom Kim

Young-Jun Yoon

Kang-Sub Kwak

Jinyeong Moon

Si-Hong Kim

Hong-Bae Kim

An operating method for a semiconductor memory device includes: generating a whole-domain-crossing-unit reset signal based on a domain-crossing-unit reset signal input to a whole-domain-crossing-unit-reset-signal generator; and resetting a counter synchronized to a data clock of a domain-crossing unit based on the whole-domain-crossing-unit reset signal during a data clock preparation section in which the data clock does not toggle.

Semiconductor memory device for resetting counter synchronized with data clock by using reset signal synchronized with system clock and method for operating the same

An apparatus for controlling a latency in a synchronous semiconductor device. The apparatus includes a first counting block for counting a cycle of a first clock signal to thereby generate a first binary code; a second counting block for counting a cycle of a second clock signal to thereby generate a second binary code. The second clock signal is obtained by delaying the first clock signal by a predetermined delay amount, A code comparison block stores the second binary code in response to a command and compares the first binary code with the second binary code to thereby generate a latency control signal.

Apparatus and method for latency control in high frequency synchronous semiconductor device

A method for adjusting a timing between an internal clock and a command in a gear down mode of a memory device includes detecting a sync pulse at rising and falling edges of the internal clock, and adjusting between the internal clock of the memory device and the command according to the detection result.

Semiconductor memory device, memory system including the same, and method for adjusting timing between internal clock and command

A semiconductor integrated circuit includes a first pad configured to receive a first voltage, a second pad configured to receive a second voltage, an internal voltage generation circuit configured to generate a third voltage having the same voltage level as the first voltage in response to the second voltage during a test mode, and an internal circuit configured to perform a normal operation using the first voltage and the second voltage during a normal mode and perform a test operation using the second voltage and the third voltage during the test mode.

Semiconductor integrated circuit

A semiconductor memory device is capable of outputting a preset logic level through an EDC pin according to an operation mode during an initial operation, and providing a stable operation according to the specification of the semiconductor memory device just after the input of a data clock (WCK). The semiconductor memory device includes an output circuit configured to output a synchronous data in response to a data clock when the data clock is enabled, and output an asynchronous data when the data clock is disabled, and a data clock detection circuit configured to control outputting the asynchronous data by checking whether the data clock is in a stable state or not.

Semiconductor memory device having capability of stable initial operation

Semiconductor device includes a pad for outputting a cyclic redundancy check (CRC) data for error detection and a signal outputting unit for outputting the CRC data or a data strobe signal, which is output together with data of being output in response to a read command, through the pad according to operation modes. Method for operating a semiconductor device provided a step of outputting a CRC data for error detection through a CRC data pad and a step of outputting a data strobe signal, which is output together with data output in response to a read command, through the CRC data pad according to an operation mode.

Semiconductor device and method for operating the same

A delay locked loop includes a first delay unit configured to output an output clock by delaying an input clock by a delay; a replica delay unit configured to output a feedback clock by delaying the output clock with a delay equal to a sum of a first delay amount for a first operational frequency of the delayed locked loop and an additional delay amount for a second operational frequency of the delayed locked loop, wherein the second operational frequency is lower than the first operational frequency; and a delay amount control unit configured to control the delay of the first delay unit by comparing a phase of the input clock with a phase of the feedback clock.

Delay locked loop and integrated circuit including the same

Semiconductor memory device for high-speed data input/output includes a first serializer configured to partially serialize input 8-bit parallel data to output first to fourth serial data, a second serializer configured to partially serialize the first to fourth serial data to output fifth and sixth serial data and a third serializer configured to serialize the fifth and sixth serial data to output seventh serial data.

Semiconductor memory device for high-speed data input/output

A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines.

Semiconductor memory device and operating method thereof

There is provided a semiconductor memory device, including: a plurality of bank groups each comprising a plurality of banks; a plurality of data pads grouped by a predetermined number for receiving data for the bank groups, wherein the data pads are divided into a plurality of first pad groups receiving data and a plurality of second pad groups selectively receiving data according to a data input/output option value; a first driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the first pad group; a second driving unit configured to drive data input via the second pad group to transfer the data input via the second pad group to the bank group corresponding to the second pad group; and a third driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the second pad group in response to the data input/output option value.

Semiconductor device

A semiconductor device includes a plurality of data driving units, each configured to drive a corresponding data output pad by a power supply voltage supplied through a power supply voltage input pin and a ground voltage supplied through a ground voltage input pin, in response to a corresponding bit of a data code, a pattern sensing unit configured to sense a bit pattern of the data code and generate a pattern sensing signal, and a phantom driving unit configured to form a current path between the power supply voltage input pin and the ground voltage input pin and to drive the current path by a driving force determined in response to the pattern sensing signal.

A circuit which can reduce time taken by a clock alignment training operation in a semiconductor memory device is provided. The semiconductor memory device, which includes: a clock inputting unit configured to receive a system clock and a data clock; a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock, wherein the clock dividing unit determines a phase of the data division clock in response to an inversion division control signal; a phase dividing unit configured to generate a plurality of multiple phase data division clocks having respective predetermined phase differences in response to the data division clock; a data serializing unit configured to serialize predetermined parallel pattern data in correspondence with the multiple phase data division clocks; and a signal transmitting unit configured to transmit an output signal of the data serializing unit to the outside.

Semiconductor memory device

A semiconductor memory device includes a clock supply portion for providing an external clock to the interior of the memory device, a clock transfer portion for transferring the clock from the clock supply portion to each of elements in the memory device and data output portions for outputting data in synchronism the clock from the clock transfer portion, wherein the clock from the clock supply portion to the clock transfer portion swings at a current mode logic (CML) level.

A data output circuit of a semiconductor memory apparatus includes: a control unit that outputs a first standby instruction signal, a second standby instruction signal, a first output instruction signal, and a second output instruction signal in response to an input of a standby instruction signal, an output instruction signal, a first test signal, and a second test signal; a first output driver that causes first data to be output or to enter a standby state according to whether or not the first standby instruction signal or the first output instruction signal is enabled; and a second output driver that causes second data to be output or to enter a standby state according to whether or not the second standby instruction signal or the second output instruction signal is enabled.

Data output circuit

A semiconductor memory apparatus capable of detecting an error in data input/output includes a memory cell block including a plurality of memory cells. A data input unit receives data from outside the semiconductor memory apparatus and performs predetermined signal processing to record the received data in the memory cell block. A first global data line is connected between the data input unit and the memory cell block. A data output unit receives data from the memory cell block and performs predetermined signal processing to output the received data to the outside of the semiconductor memory apparatus. A second global data line is connected between the memory cell block and the data output unit. A multiplexer selectively outputs data from the first or second global data line in response to a control signal. An error detection code generator generates an error detection code having a plurality of bits to detect whether the data output from the multiplexer includes an error, and outputs the error detection code to the outside of the semiconductor memory apparatus.

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Gyeonggi-do, South Korea

Sang-Sic Yoon