Skhynix Inc.

Hideep Inc.

Hynix Semiconductor Inc.

Sang Sic Yoon

Bon Kee Kim

Kyung Hoon Kim

Kyu Dong Hwang

Hwan Hee Lee

Jung Taek You

Myung Jun Jin

Se Yeob Kim

Seung Hun Lee

Seyeob Kim

Bonkee Kim

Tae Yong Lee

Young Jun Park

Saeng Hwan Kim

Young Jun Ku

Young Ick Cho

Bong Jin Seo

Ho Jun Moon

Hong Bae Kim

Hong Joo Song

Chae Sung Lim

Woongrae Kim

Choung Ki Song

Min Su Park

Hyun Seung Kim

Dong Kyun Kim

Jin Youp Cha

Soo Young Jang

Kwang Hun Lee

Yong Gu Kang

Yu Ri Lim

Yoo Jong Lee

Won Lee

Kang Sub Kwak

Keun Soo Song

Jae Bum Jun

Yun Joung Kim

Gyung Tae Kim

Young Do Hur

Bo Kyeom Kim

In Keun Kim

Seon Dong Kwak

Sun Young Kwon

A semiconductor device includes a driving signal generation circuit configured to generate a pull-up driving signal that is enabled when a data clock input control signal is input during a normal operation, configured to generate a pull-down driving signal that is enabled when any one of a write signal and a read signal is input, and configured to generate the pull-down driving signal that is enabled after a set interval when a synchronization signal is input, and a sync enable signal generation circuit configured to generate a sync enable signal for receiving a data clock from a time at which the pull-up driving signal is enabled to a time at which the pull-down driving signal is enabled.

Semiconductor system

A memory system includes a memory controller and a memory device. The memory controller accesses the memory device by providing a system clock signal, a data clock signal, and a chip selection signal and provides a data clock enable signal to the memory device after the access to the memory device. The memory device communicates with the memory controller based on the system clock signal, the data clock signal, and the data clock enable signal.

Memory system related to clock synchronization

A semiconductor device includes a command pulse generation circuit configured to generate a first command pulse in synchronization with a frequency division clock and to generate a second command pulse in synchronization with an inverted frequency division clock, based on a test write command. The semiconductor device also includes an alignment data generation circuit configured to align first internal data in an in-phase manner to generate first alignment data, based on the first command pulse, and to align second internal data in an out-of-phase manner to generate second alignment data, based on the second command pulse. The semiconductor device further includes a phase detection circuit configured to determine synchronization states of a clock and the frequency division clock, based on the first alignment data and the second alignment data.

Semiconductor devices and semiconductor systems related to synchronization between clocks

A semiconductor system according to an embodiment of the present disclosure includes a controller configured to output a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device, including a first rank and a second rank, configured to receive the command address, the first chip selection signal, and the second chip selection signal and configured to calibrate each termination resistance value based on the command address, the first chip selection signal, and the second chip selection signal. The first rank calibrates the termination resistance value of the first rank to a target resistance value based on the command address and the first chip selection signal when a write operation on the first rank is performed, and the first rank calibrates the termination resistance value of the first rank to a dynamic resistance value based on the second chip selection signal when a write operation on the second rank is performed.

Semiconductor devices and semiconductor systems calibrating termination resistance

A semiconductor device includes a selection input circuit and a core data generation circuit. The selection input circuit is configured to generate selection data, a selection parity, and a selection data control signal from data, a parity, and a data control signal during a write operation and sets the selection data, the selection parity, and the selection data control signal to a predetermined logic level during a pattern write operation. The core data generation circuit is configured to receive drive data, a drive parity, and a drive data control signal driven by the selection data, the selection parity, and the selection data control signal to generate core data which are stored into a memory core according to whether an error correction operation and a data inversion operation is performed.

Semiconductor devices

A semiconductor system includes a controller configured to apply a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device including a first rank and a second rank configured to calibrate each termination resistance, based on the command address, the first chip selection signal, and the second chip selection signal.

Semiconductor device related to calibrating termination resistance

A semiconductor system includes a controller configured to transmit a command address and a plurality of read strobe signals, and a semiconductor device including a first rank and a second rank that are configured to receive the command address and the plurality of read strobe signals and to perform a write operation and a read operation based on the command address. In the semiconductor device, the first rank is configured to calibrate a termination resistance value of the first rank to a target resistance value when a write operation for the first rank is performed. In the semiconductor device, the first rank is configured to calibrate the termination resistance value of the first rank to a dynamic resistance value based on the plurality of read strobe signals when a write operation for the second rank is performed.

Semiconductor device related to calibrating a termination resistance

A memory device includes a first data strobe pad; a strobe signal generation circuit suitable for generating a read data strobe signal based on a read timing signal; a monitoring receiver suitable for receiving the read data strobe signal fed back through the first data strobe pad according to a monitoring enable signal; a sampler suitable for generating a sampling clock by sampling the fed back read data strobe signal according to a random clock; a first counter suitable for generating a first counting signal by counting the random clock; a second counter suitable for generating a second counting signal by counting the sampling clock; and a duty detector suitable for generating a duty ratio detection signal based on the first counting signal and the second counting signal.

Stacked semiconductor device and semiconductor system including the same

A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.

Stacked memory device and test method thereof

A semiconductor system includes a semiconductor device and a controller. The semiconductor device includes a first memory rank and is configured to perform, in response to receiving a first write command, a first write operation of writing first data to the first memory rank. The semiconductor device includes a second memory rank and is configured to perform, in response to receiving a second write command, a second write operation of writing second data to the second memory rank. The controller is configured to receive at least one write request and responsively generate the first and second write commands separated in time so that a transition time interval between generation of the first write command and generation of the second write command is based on the second memory rank being different from the first memory rank and based on a comparison of a write preamble period to a write post-amble period.

Methods, controllers, and semiconductor systems for generating write commands

A semiconductor device includes a power gating control block and a power gating circuit. The power gating control block activates a data power control signal during a period that is set by a target code, the period being from a point in time in which the semiconductor device enters a read mode or a write mode. In addition, the power gating control block deactivates an operation power control signal in a power-down mode. The power gating circuit inhibits a data power signal from being supplied to a data input/output block based on the data power control signal. Moreover, the power gating control block inhibits an operation power signal from being supplied to an internal operation control block based on the operation power control signal.

Semiconductor device with a power-down mode and a power gating circuit and semiconductor system including the same

A semiconductor device includes a read control circuit configured to generate first and second output control signals including pulses which are selectively generated, from first and second strobe signals depending on burst information; and a data output circuit configured to latch first internal data depending on the pulse of the first output control signal, transfer second internal data at a time when the second output control signal level-transitions, and generate output data from the latched first internal data and the transferred second internal data.

Data output method and semiconductor device using the data output method

In one embodiment, a touch sensor includes a first electrode, a second electrode, and a spacer layer located between the first electrode and the second electrode. One of the first electrode and the second electrode is a drive electrode to which a drive signal is applied. The other one of the first electrode and the second electrode is a receiving electrode that receives the drive signal by a mutual capacitance between the first electrode and the second electrode. When an external pressure is applied to the first electrode through a display, the first electrode is concavely bent toward the second electrode. The mutual capacitance between the first electrode and the second electrode changes according to a distance between the first electrode and the second electrode. The magnitude of the external pressure according to the change of the capacitance between the first electrode and the second electrode is detected.

Touch sensor

A semiconductor apparatus may include a logic circuit and a power control circuit. The logic circuit operates by being supplied with power through a power line. The power control circuit includes a plurality of power switches, and supplies a first power supply voltage and a second power supply voltage to the power line. When a mode of the semiconductor apparatus is changed, the power control circuit causes the plurality of power switches to sequentially stop supplying one of the first power supply voltage and the second power supply voltage to the power line, and then causes the plurality of power switches to sequentially supply the other of the first power supply voltage and the second power supply voltage to the power line.

Power control circuit and semiconductor apparatus including the power control circuit

Growing community of inventors

Gyeonggi-do, South Korea

Sang Sic Yoon