Samsung Electronics Co., Ltd.

Sang-seok Kang

Jae-hoon Joo

Jong-hyoung Lim

Jin-seok Lee

Byung-Heon Kwak

Jeong-ho Bang

Hong-Beom Kim

Kwang-kyu Bang

Kyeong-seon Shin

Yong-Jin Park

Cheol-Hong Park

Ho-jeong Choi

Hyen-wook Ju

Chang-hag Oh

Jeon-hyung Lee

Gwang-young Kim

Kyung-moo Kim

A fuse box including make-links and a redundancy address decoder including the fuse box are provided. It is preferable that the fuse box includes a plurality of make-links for programming an address of a defective normal memory cell with an address of a corresponding redundant memory cell, and the address is a row address or a column address. The redundant address decoder includes a fuse box having a plurality of make-links for decoding an address of a defect cell and a redundant word line selection circuit for selecting a word line of a redundant cell corresponding to the address of the defect cell in response to a signal output from the fuse box.

Fuse box including make-link and redundant address decoder having the same, and method for repairing defective memory cell

An integrated circuit includes first and second pads that are electrically connected to a circuit inside the integrated circuit. The circuit performs multiple functions which may be selected. A function identification circuit, inside the integrated circuit, is electrically connected to the first and second pads. The function identification circuit operates in multiple modes, wherein each operating mode corresponds to a function performed by the circuit. The function of the circuit may thereby be identified using fewer pads which may allow a reduction in the cost of the integrated circuit.

Integrated circuits including function identification circuits having operating modes that identify corresponding functions of the integrated circuits

A semiconductor memory device for sequentially disabling activated word lines is provided. The semiconductor memory device having a plurality of word lines connected to a plurality of memory cells includes a predecoding unit for predecoding a row address received from the outside, a row decoding and word line driving block, which is connected to the predecoding unit and the plurality of word lines, for decoding an output of the predecoding unit, selecting some of the plurality of word lines, and activating the selected word lines and a controller connected to the predecoding unit and the row decoding and word line driving block, for receiving the row address, the output of the predecoding unit, and at least one control signal, generating at least one output signal, and sequentially disabling the activated word lines by enabling the at least one output signal in response to the row address and the output of the predecoding unit.

Semiconductor memory device having sequentially disabling activated word lines

An integrated circuit memory device includes a memory cell array and first and second sense amplifiers positioned on respective opposite first and second sides of the memory cell array. A first bit line pair and a second bit line pair connect the memory cell array to the first and second sense amplifiers, respectively. A first bit line of the first bit line pair and a first bit line of the second bit line pair extend across the memory cell array from the first side to the second side without crossing one another. A second bit line of the second bit line pair extends across the memory cell array from the first side to the second side, crossing the first bit line of the first bit line pair and the first bit line of the second bit line pair.

Integrated circuit memory devices with improved twisted bit-line

Multi-bank integrated circuit memory devices include first and second memory cell arrays having first and second pairs of differential bit lines electrically coupled thereto, respectively. A dual sense amplifier is also provided and this sense amplifier is electrically coupled together by a first pair of differential input/output lines. First and second isolation circuits are also provided. The first isolation circuit is electrically coupled to the first pair of differential bit lines and is responsive to a first control signal (C1). The second isolation circuit is electrically coupled to the second pair of differential bit lines and is responsive to a second control signal (C2). First and second equalization circuits are provided. The first equalization circuit is responsive to the second control signal and performs the function of equalizing a potential of the first pair of differential bit lines. The second equalization circuit is responsive to the first control signal and performs the function of equalizing a potential of the second pair of differential bit lines. These first and second control signals are generated by a control signal generator, in response to a row address.

Multi-bank integrated circuit memory devices having cross-coupled

A burn-in stress circuit for a semiconductor memory device. A burn-in enable signal generator generates a burn-in enable signal in response to a plurality of control signals. A wordline predecoder generates a wordline driving voltage for driving a wordline in response to the burn-in enable signal and another a plurality of control signals. A wordline decoder applies the wordline driving voltage to the wordline in response to the burn-in enable signal and another plurality of control signals. To reduce the stress testing time by stressing multiple rows of a memory array simultaneously, all of the wordlines (rows) are stressed and or tested at the same time. To select all of the wordlines, the wordlines are selected sequentially, but each selected wordline is held in a selected state by a latching mechanism while all of the other wordlines are being selected as well. When all of the wordlines (or a desired subset) have been selected, the burn-in stress test begins.

Burn-in stress circuit for semiconductor memory device

An internal voltage conversion circuit for a DRAM wherein a voltage level of an internal power supply is regulated by an external signal applied to the DRAM pins after packaging to perform reliability tests. The internal voltage conversion circuit includes a test mode signal generator, for generating a test mode signal by combining first control signals applied externally of the semiconductor device, and a switching signal generator, for generating first and second switching signals according to second control signals applied externally of the DRAM when the test mode signal is active. First and second switching resistor portions connected in series between the internal power supply port and a ground potential are switched by the first and second switching signals, respectively, so that their resistance values are changed. The resistor portions are in a feedback path connected to one input of a comparator. The other input is connected to a reference cell. The internal voltage supply varies responsive to changes in resistance values.

Circuit for converting internal voltage of semiconductor device

A voltage clamping circuit for a semiconductor memory device which is capable of rapidly coping with the demand of the user. The voltage clamping circuit includes PMOS transistors connected in series between an external supply voltage terminal and a node on an output line of a DC voltage generator, a control PMOS transistor having a channel connected at both ends thereof respectively to the node on the output line and a node between the second and third ones of the series-connected PMOS transistors, and a pad connected to a control electrode of the control PMOS transistor. The pad is selectively connected to a supply voltage in a first state and to a ground voltage in a second state, thereby controlling a clamping interval of the clamping means to be variable. The first state is a state requiring a longer clamping interval than that of the second state.

Voltage clamping circuit for semiconductor devices

Integrated circuit memory devices contain an array of active memory cells and at least one column of dummy memory cells having missing electrical connections to either a dummy bit line and/or respective storage electrodes. The dummy memory cells are provided with missing electrical connections so that formation of stray electrical 'shorts' between storage electrodes of dummy and active memory cells during fabrication do not cause memory failures when the memory devices are installed. In particular, integrated circuit memory devices are provided which comprise an array of active DRAM memory cells and a column of dummy DRAM memory cells. The active DRAM memory cells each contain electrical connections to a respective active bit line and a respective storage electrode, but the dummy DRAM memory cells are each devoid of an electrical connection to a dummy bit line and/or a respective storage electrode. Accordingly, the formation of a stringer (e.g., electrical short) between a storage capacitor of an active memory cell and a dummy memory cell does not result in a memory failure even if the word line coupled to the dummy memory cell is activated and the dummy bit line is biased at a potential which is different from the potential of the storage capacitor of the active memory cell.

Growing community of inventors

Youngin, South Korea

Sang-seok Kang