Samsung Electronics Co., Ltd.

Sang-Seok Kang

Jong-hyun Choi

Jae-Hoon Joo

Jong-Hyoung Lim

Sang-Man Byun

Jong-Hyun Choi

Kyu-Nam Lim

Hyung-Dong Kim

Yun-Sang Lee

Young-Man Ahn

Yun-sang Lee

Jin-Seok Lee

Dong-min Kim

Jae-woong Lee

Cheol-Hong Park

Dan-Kyu Kang

Choong-Sun Park

Min-Ki Hong

Yong-Hwan Jung

Young-Hee Jung

Sun-Young Lee

Hyun-Soo Kim

Seong-Jin Jang

Sung-Min Hwang

Hyun-Seok Lee

Byung-chul Kim

Kyu-Chan Lee

Jei-Hwan Yoo

Chi-wook Kim

Soo-In Cho

Jong-hoon Kim

Jeong-ho Bang

Jong-hyoung Lim

Woo-seop Kim

Kyeong-Seon Shin

Hong-Beom Kim

Ki-Sang Kang

Jong-Eon Lee

Kyeong-seon Shin

Sang-Ki Hwang

Kwang-kyu Bang

Choong-sun Shin

Ho-jeong Choi

Kang-Young Cho

Byung-Heon Kwak

Hyen-wook Ju

Byung-heon Kwak

Boo-Jin Kim

Chang-hag Oh

Young-Ok Cho

Jung-kuk Lee

Boa-Yeong Oh

Kyoung-Moo Kim

Sei-Hui Lee

Chang-Joo Choi

Byung-Il Ryu

Disclosed are a dynamic random access memory (DRAM) device, an on-die termination (ODT) resistance value setting method thereof, and a computer program therefor, and the DRAM device includes at least one DRAM module and a memory controller configured to measure a resistance value of an ODT resistor corresponding to one of a rank included in the DRAM module, a chipset included in the rank, and a DQ included in the chipset and set a resistance value of an ODT resistor corresponding to one of the rank, the chipset, and the DQ on the basis of the measured resistance value.

DRAM device and ODT resistor value adjustment method and computer program for the same

A memory module is provided. A plurality of DRAMs is mounted on a PCB. At least one DRAM has an operating parameter different from other DRAMs according to a position where the at least one DRAM is mounted on the PCB.

Memory device, memory module including the memory device, method of fabricating the memory module, and method of repairing the memory module

A memory module includes a first rank, a second rank and a test control unit. The first rank includes a plurality of semiconductor memory devices configured to operate in response to a first chip selection signal. The second rank includes a plurality of semiconductor memory devices configured to operate in response to a second chip selection signal. The test control unit is configured to simultaneously enable the first and second chip selection signals to test the first and second ranks in a test mode.

Memory module and a memory test system for testing the same

Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.

Fuse circuit and semiconductor device having the same

A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed.

Semiconductor memory devices including burn-in test circuits

A semiconductor memory device includes a voltage level selection unit configured to output a plurality of voltage level selection signals according to a fuse program in response to a self-refresh command signal and a reference voltage generator configured to receive a reference voltage and output a target reference voltage having a different voltage level depending on a normal mode or a self-refresh mode in response to the voltage level selection signals.

Semiconductor memory device

A semiconductor memory device having dummy sense amplifiers and a method of utilizing the same are provided. Embodiments of the semiconductor memory device may include at least one dummy cell block including dummy cells and memory cells. Normal bit lines connecting the memory cells in the dummy cell block in a first direction and dummy bit lines connecting the dummy cells in the first direction. A dummy sense amplifier is also included for connecting any two of the normal bit lines and the dummy bit lines. Some of the embodiments may improve the sensing margin and refresh margin in sensing memory cells in the dummy cell, as well as increasing the redundancy efficiency and utilization of the dummy cells.

Semiconductor memory device having dummy sense amplifiers and methods of utilizing the same

A semiconductor memory device and method directed to performing a memory operation in a semiconductor memory device are provided. The method includes receiving a write command signal from a memory controller; receiving data from the memory controller, the data including n pieces of data, wherein the k-th piece of data comprises masking data to be masked; and receiving a data masking signal from the memory controller, the data masking signal including enable information that enables data masking, and non-enable information for not enabling data masking, wherein the enable information is used to mask the k-th piece of data. A latency between receiving the write command signal and receiving the enable information is less than a latency between receiving the write command and receiving the k-th piece of data.

Semiconductor memory device and method of performing a memory operation

A semiconductor memory device is provided. The device includes an on die termination circuit controlling a termination resistance value by detecting a phase change of a signal inputted through a pad. Additionally, the on die termination circuit changes the termination resistance value when an identical phase signal is inputted during n (n is positive integer) periods of a clock signal.

Semiconductor memory device including on die termination circuit and on die termination method thereof

A semiconductor memory device and method directed to performing a memory operation in a semiconductor memory device, which include receiving data and a data masking signal corresponding to a portion of the received data configured to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory, and further configuring different timing parameters of the received data and the data masking signal for executing the write command without writing the at least a portion of the received data into the memory.

A semiconductor memory device performs a parallel bit test on a plurality of memory blocks by writing test pattern data into the plurality of memory blocks, outputting two bits from each memory block in parallel and comparing the two bits output from each memory block with each other in a first test mode, and outputting two bits from respectively different memory blocks and comparing the two bits output from the respectively different memory blocks with each other in a second test mode.

Parallel bit test circuit and method for semiconductor memory device

A semiconductor device comprises a plurality of banks, a plurality of control circuits, and a plurality of temperature sensors, wherein each of the plurality of temperature sensors is disposed near at least one of the plurality of banks for sensing the temperature of the area surrounding the at least one of the plurality of banks and for outputting a sense signal corresponding to a sensed temperature, and each of the plurality of control circuits outputs at least one control signal, for controlling an operation of the at least one of the plurality of banks, to the at least one of the plurality of banks based on the sense signal.

Semiconductor device having a plurality of temperature sensors and semiconductor device control method using the plurality of temperature sensors

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Suwon-si, South Korea

Sang-Seok Kang