Samsung Electronics Co., Ltd.

Sang-Ryol Yang

Ki-Hyun Hwang

Jin-Gyun Kim

Jin-Tae Noh

Ju-Wan Lim

Ji-Eun Lee

Si-Young Choi

Ki-chul Kim

Han-Mei Choi

Young-Seok Kim

Bon-Young Koo

Jae-young Ahn

Jung-Min Oh

Ji-Hoon Choi

Bong-jin Kuh

Jung-Ho Kim

Myoung-Bum Lee

Byung-Hong Chung

Hong-suk Kim

Je-Woo Han

Gyung-Jin Min

Yong-Woo Hyung

Hun-hyeong Lim

Jae-Jin Shin

Man-Sug Kang

Hee-Seok Kim

Yoo-Chul Kong

Si-Hyung Lee

Jong-sung Lim

Jun-ho Yoon

Sung-Hae Lee

Sang-Yoon Woo

Sung-kweon Baek

Yong-Moon Jang

Tae-Jin Park

Young-Sub Yoo

Hyun-Seok Jang

Jin-Tae No

Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.

Method of fabricating semiconductor device

In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.

Methods of manufacturing semiconductor devices

A flash memory device including a lower tunnel insulation layer on a substrate, an upper tunnel insulation layer on the lower tunnel insulation layer, and a P-type gate on the upper tunnel insulation layer, wherein the upper tunnel insulation layer includes an amorphous oxide layer.

Flash memory device including multilayer tunnel insulator and method of fabricating the same

Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

Three dimensional semiconductor memory device and method of fabricating the same

A method of fabricating a non-volatile memory device includes forming an isolation trench in a semiconductor substrate, and the isolation trench defines first and second fins. The method further includes forming an isolation layer partially filling the isolation trench, forming first and second charge trap patterns respectively covering parts of the first and second fins projecting from the isolation layer, and forming a control gate electrode covering the first and second charge trap patterns and crossing the first and second fins.

Method of fabricating non-volatile memory device having separate charge trap patterns

Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine ions from the application of a TiN metal gate, and a method of fabricating the semiconductor device. The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line by which the trench may be buried on the surface of the gate electrode layer.

Semiconductor having buried word line cell structure and method of fabricating the same

A method for forming a low-k dielectric layer for a semiconductor device using an ALD process including (a) forming predetermined interconnection patterns on a semiconductor substrate, (b) supplying a first and a second reactive material to a chamber having the substrate therein, thereby adsorbing the first and second reactive materials on a surface of the substrate, (c) supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, (d) supplying a third reactive material to the chamber, thereby causing a reaction between the first and second materials and the third reactive material to form a monolayer, (e) supplying a second gas to the chamber to purge the third reactive material that remains unreacted in the chamber and a byproduct; and (f) repeating (b) through (e) a predetermined number of times to form a SiBN ternary layer having a predetermined thickness on the substrate.

Method for forming a low-k dielectric layer for a semiconductor device

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Hwaseong-si, South Korea

Sang-Ryol Yang