Samsung Electronics Co., Ltd.

Sang-rok Hah

Bo-un Yoon

Hong-Seong Son

Jung-Yup Kim

Kun-tack Lee

Young-rae Park

Kyung-Hyun Kim

Jae-Dong Lee

Jong-won Lee

Il-Goo Kim

Im-Soo Park

Jeong-Lim Nam

Yong-pil Han

Hong-kyu Hwang

Chang-ki Hong

Kyoung-woo Lee

Kwang-bok Kim

Jae-Phil Boo

Ja-Eung Koo

Sun-Yong Lee

Young-min Kwon

Seung-chul Kim

In-jun Yeo

Hyun-ho Jo

Sung-Bae Lee

Byoung-moon Yoon

Duk-Ho Hong

Moo-Yong Park

Jong-Gyoon Kim

Ja-Hyung Han

Won-bae Jang

Chan-seung Choi

Min-suk Kim

Chee-wan Kim

Byung-Lyul Park

Jong-Won Lee

Dong-jun Kim

Byoung-Moon Yoon

Min-Soo Cho

Jeong-sic Jeon

Wan-jae Park

Eui-Youl Ryu

Hyo-Jong Lee

Hyung-Ho Ko

Kyu-hwan Chang

Jun-Hwan Oh

Ja-hyung Han

Young-Hee Kim

Seung-Gun Lee

Kwang-wook Lee

Ui-hyoung Lee

Woo-gwan Shim

Hyun-Ho Cho

Kwang-Bok Kim

Kyoung-mo Yang

Yi-Gwon Kim

Jun-shik Bae

Gi-jong Park

In-Ryong Kim

Gee-won Nam

Sung-ki Shin

Sae-il Son

In-Jun Yeo

Ju-Hyuk Chang

Ho-Sen Chang

Dai-Goun Kim

Bo-an Yoon

Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.

Semiconductor process evaluation methods including variable ion implanting conditions

An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.

Inductor for a system-on-a-chip and a method for manufacturing the same

Polishing apparatus and related methods employ aligned first and second magnetic field sources to adjust the compressive force and/or pressure applied by a carrier head against a target workpiece (such as a wafer) by selectively and controllably generating a repellant or attractive force between the two magnetic field sources.

Polishing apparatus and related polishing methods

An apparatus for cleaning a semiconductor wafer and method for cleaning a wafer using the same wherein, the apparatus includes a chamber on which a wafer is mounted, a revolving chuck mounted in the chamber for supporting and fixing the wafer, a nozzle for spraying cleaning solution onto the wafer, a cover for covering an upper part of the chamber, and a light source. The cleaning solution, preferably one of ozone water, hydrogen water, or electrolytic-ionized water, may be heated for a short time and used to clean the wafer.

Apparatus for cleaning semiconductor wafer including heating using a light source and method for cleaning wafer using the same

A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same

A method for use in manufacturing a semiconductor device includes forming a photoresist pattern on a substrate, performing first etching process in which an initial trench is formed using the photoresist pattern as a mask, and performing second distinct etching process to enlarge the initial trench. Thus, the initial trench can be formed using the photoresist pattern having a stable structure. Thereafter, the trench is enlarged using an etching solution having a composition based on the material in which the initial trench is formed, e.g., a silicon substrate or an insulation film. Therefore, a metal wiring, an isolation film or a contact can be formed in the enlarged trench to desired dimensions.

Method of forming a trench for use in manufacturing a semiconductor device

Various methods are provided for forming metal interconnection layers of semiconductor devices. One exemplary method for forming a metal interconnection layer of a semiconductor device includes forming an interlayer dielectric layer on a substrate, forming a hard mask layer on the interlayer dielectric layer, wherein the hard mask layer serves as an anti-reflection layer, depositing and patterning a first photoresist layer to form a first photoresist pattern on the hard mask layer, forming a partial via hole in the interlayer dielectric layer by etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask, removing the first photoresist pattern, depositing a second photoresist layer to fill the partial via hole with photoresist material and patterning the second photoresist layer to form a second photoresist pattern that defines a trench interconnection area which overlaps at least portion of the partial via hole, etching the hard mask layer using the second photoresist pattern as an etching mask to form a hard mask pattern, completely removing the second photoresist pattern and the photoresist material in the partial via hole, etching the interlayer dielectric layer using the hard mask pattern as an etching mask to form the trench interconnection area and to extend the partial via hole to form a full via hole, and filling the full via hole and the trench interconnection area with a conductive material.

Method of forming metal interconnection layer of semiconductor device

The present application discloses a method of cleaning a semiconductor wafer by mounting a wafer to a chuck, positioning a gas guard, defining therein a chamber having an open bottom, immediately above the layer of water, spraying de-ionized water onto the wafer while rotating the chuck at a location outside the chamber when the wafer is mounted to the chuck, to thereby form a layer of water on the wafer, and spraying a cleaning gas from a gas spraying unit disposed above said chuck through the chamber and into the layer of water to thereby cause the cleaning gas to dissolve in the layer of water, and at the same time moving the chamber across a surface of the wafer, to thereby clean the wafer, wherein said gas spraying unit includes a gas injection tube oriented to inject the cleaning gas towards the wafer mounted to the chuck, and the gas guard connected to the gas injection tube.

Method of cleaning semiconductor wafer

A polishing slurry including an abrasive, deionized water, a pH controlling agent, and polyethylene imine, can control the removal rates of a silicon oxide layer and a silicon nitride layer which are simultaneously exposed during chemical mechanical polishing (CMP) of a conductive layer. A relative ratio of the removal rate of the silicon oxide layer to that of the silicon nitride layer can be controlled by controlling an amount of the choline derivative.

Chemical mechanical polishing slurry

A cleaning solution for use in removing a damaged portion of a ferroelectric layer, and a cleaning method using the solution. The cleaning solution includes a fluoride, an organic acid with carboxyl group, an alkaline pH adjusting agent and water.

Cleaning solution for removing damaged portion of ferroelectric layer and cleaning method using the same

The apparatus for cleaning a wafer includes an energy concentration relieving member positioned at the side of the wafer. An elongated portion of a probe extends over and substantially parallel to the wafer surface. A vibrator is attached to a rear end of the probe for vibrating the probe such that the elongated portion transfers acoustic vibrational energy to the wafer and dislodges debris.

Apparatus and method for cleaning a semiconductor wafer

A dual damascene process is disclosed. According to the dual damascene process of the present invention, a first recessed region through an intermetal dielectric layer is filled with a bottom protecting layer, and the bottom protecting layer and the intermetal dielectric layer are simultaneously etched to form a second recessed region that has a shallower depth and wider width than the first recessed region on the first recessed region by using an etch gas selectively etches the intermetal dielectric layer with respect to the bottom protecting layer. In other words, the etch selectivity ratio, the intermetal dielectric layer with respect to the bottom protecting layer, is preferably about 0.5 to about 1.5. Thus, it is possible to form a dual damascene structure without the formation of a byproduct or an oxide fence.

Dual damascene process

In a method for filling a hole with a metal, an insulating layer, a first mask layer and a second mask layer are successively formed on a semiconductor substrate. The first and second mask layers are etched using a photoresist pattern to form first and second masks. The first mask layer pattern is selectively etched using an etchant, the first mask layer pattern having a higher etching selectivity than the second layer pattern with respect to the etchant, to form a third mask layer pattern having a broadened opening. The insulating layer is etched using the second mask to form a hole in the insulating layer. A metal layer is formed in the hole and the third opening. The metal layer is planarized to form a metal plug buried in the hole without recesses or voids.

Method for filling a hole with a metal

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Seoul, South Korea

Sang-rok Hah