Skhynix Inc.

Hynix Semiconductor Inc.

Sang-Mook Oh

Jae-Hyuk Im

Tae-Sik Yun

A semiconductor memory device includes a plurality of banks; a plurality of word lines; an advanced refresh operation mode where two or more word lines are selected in parallel in each bank; a pulse generation unit suitable for generating a single bank refresh pulse that toggles for a given time in response to a single bank refresh command of a single bank refresh operation mode; and an address generation unit suitable for generating an advanced single bank address for selecting at least two word lines in one of the banks in response to the single bank refresh pulse and an input address in an entry section of the advanced refresh operation mode.

Semiconductor memory device

A semiconductor integrated circuit includes at least one second semiconductor chip configured to generate an internal voltage, and a first semiconductor chip including a monitoring unit configured to monitor the internal voltage, and a first pad configured to provide monitoring result information outputted from the monitoring unit to a test device.

Semiconductor integrated circuit and method for measuring internal voltage thereof

A signal transmission/reception system includes a transmission line, a signal transmission circuit configured to generate a transfer signal and transfer the transfer signal through the transmission line, wherein a logic value of the transfer signal is changed whenever a pulse signal is input to the signal transmission circuit, and a signal reception circuit configured to receive the transfer signal through the transmission line and generate a restoration signal using the transfer signal and a delayed transfer signal obtained by delaying the transfer signal.

Signal transmission/reception system

A semiconductor integrated circuit includes: a normal fuse cell array programmed with a normal fuse data; a dummy fuse cell array programmed with a verifying fuse data; and a sensor configured to read the verifying fuse data from the dummy fuse cell array and read the normal fuse data from the normal fuse cell array, wherein the normal fuse cell array is configured to be read according to a reading result of the dummy fuse cell array.

Semiconductor integrated circuit having array E-fuse and driving method thereof

A power-up signal generation circuit includes a power-up signal generator configured to enable a power-up signal when a level of an external power voltage is higher than a target level, and a target level controller configured to change the target level in response to a current consumption signal indicating a current consumption of a system including the power-up signal generation circuit.

Growing community of inventors

Gyeonggi-do, South Korea

Sang-Mook Oh