Samsung Electronics Co., Ltd.

Hyundai Motor Company

Kia Motors Corporation

Kia Corporation

Sang-min Shin

Young-Soo Park

Yoon-Dong Park

Sang-jin Park

June-mo Koo

Kwang-soo Seol

Yoon-dong Park

Sang-Moo Choi

Sun-ae Seo

Yoon-kyoung Cho

In-Jun Hwang

Won-joo Kim

Choong-Rae Cho

In-seok Kang

Ju-hee Park

Suk-pil Kim

Bon-jae Koo

Dongwon Kim

Hoon Moo Choi

Jung-Hoon Lee

Jung-hyun Lee

Dongjin Park

I-hun Song

Suk-Pil Kim

Won-Joo Kim

Yong-Su Kim

Byoung-Jae Bae

Jae-woong Hyun

Eun-hong Lee

Yo-sep Min

Sung-Dae Cho

Jae-Wan Park

Sun-Ae Seo

Yong-wook Kim

Young-Kwan Cha

Yong-kyun Lee

Choong-rae Cho

Seung-Hyuk Chang

Bo-soo Kang

Geun-bae Lim

Nara Cho

Tae-won Noh

Dae-in Choi

Gang-heok Kim

Jong-gul Yoon

Deok-young Kim

A strap center fixed type resonator may include a resonator body configured to be mounted on a rim portion of a wheel supporting a tire; a resonating portion formed on a surface of the resonator body; and a strap inserting portion formed on a bottom internal surface of the resonating portion inside the resonating portion to allow a strap to be inserted in the strap inserting portion, wherein the strap is inserted into the strap inserting portion to fix the resonator body to the rim portion of the wheel.

Strap center fixed type resonator and wheel assembly comprising ihe same

Provided are an electronic device and method for assisting driving of a vehicle, the electronic device including a sensor configured to sense a rotation direction of a steering wheel of the vehicle, a processor configured to monitor rotation direction switching events of the steering wheel, obtain a rotation direction switching pattern about a number of rotation direction switching events of the steering wheel per unit time, and determine whether to provide an alert to a driver of the vehicle, based on the obtained rotation direction switching pattern, and an outputter configured to output the alert to the driver, based on the determination.

Electronic device for assisting driving of vehicle and method therefor

Various embodiments of the present disclosure relate to an apparatus and a method for communicating with another electronic device in an electronic device. The electronic device includes: a first communication module configured to support low frequency communication; a second communication module configured to support cellular communication; at least one sensor; at least one processor; and a memory electrically connected with the processor, wherein, when being executed, the memory may store instructions that cause the at least one processor to detect a motion of the electronic device based on the at least one sensor, and to transmit a signal for controlling an activation state regarding the low-frequency communication with another electronic device to the another electronic device via the second communication module, based on motion information of the electronic device. Other embodiments are possible.

Electronic device for controlling vehicle, and operating method thereof

Provided are a method of and an apparatus for rapidly and effectively mixing fluids even in a laminar flow regime with a very low Reynold's number by applying AC power with a resonant frequency to more effectively induce electrokinetic instability. Also provided are a method of and an apparatus for mixing fluids in which the degree of mixing of the fluids can be varied with time by applying AC power with a lower frequency than a resonant frequency to synchronize a pattern of mixing fluids with the AC power.

Method of mixing fluids and mixing apparatus adopting the same

A ferroelectric capacitor having a three-dimensional structure, a nonvolatile memory device having the same, and a method of fabricating the same are provided. The ferroelectric capacitor may include a trench-type lower electrode, at least one layer formed around the lower electrode, a ferroelectric layer (PZT layer) formed on the lower electrode and the at least one layer and an upper electrode formed on the ferroelectric layer. The at least one layer may be at least one insulating interlayer and the at least one layer may also be at least one diffusion barrier layer. The at least one layer may be formed of an insulating material excluding SiOor may have a perovskite crystal structure excluding Pb.

Ferroelectric capacitor having three-dimensional structure, nonvolatile memory device having the same and method of fabricating the same

Provided are a charge trap semiconductor memory device including a charge trap layer on a semiconductor substrate, and a method of manufacturing the charge trap semiconductor memory device. The method includes: (a) coating a first precursor material on a surface of a semiconductor substrate to be deposited and oxidizing the first precursor material to form a first layer formed of an insulating material; (b) coating a second precursor material formed of metallicity on the first layer; (c) supplying the first precursor material on the surface coated with the second precursor material to substitute the second precursor material with the first precursor material; and (d) oxidizing the first and second precursor materials obtained in (c) to form a second layer formed of an insulating material and a metal impurity, and (a) through (d) are performed at least one time to form a charge trap layer having a structure in which the metal impurity is isolated in the insulating material.

Charge trap layer for a charge trap semiconductor memory device and method of manufacturing the same

A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.

Semiconductor memory device including recessed control gate electrode

A semiconductor memory device may include a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer between the control gate electrode and the semiconductor substrate, a tunneling insulating layer between the storage node layer and the semiconductor substrate, a blocking insulating layer between the storage node layer and the control gate electrode, and first and second channel regions surrounding the control gate electrode and separated by a pair of opposing separating insulating layers. A method of operating the semiconductor memory device may include programming data in the storage node layer by charge tunneling through the blocking insulating layer, thus achieving relatively high reliability and efficiency.

Method of operating a semiconductor memory device having a recessed control gate electrode

A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node.

Semiconductor memory device with dual storage node and fabricating and operating methods thereof

A ferroelectric capacitor comprises a first electrode comprising an alloy containing a first element and a second element of the periodic table of the elements, the first element being selected from the group consisting of Ir and Ru. A ferroelectric layer is disposed on the first electrode, wherein the ferroelectric layer comprises a ferroelectric material containing the second element. A second electrode is disposed on the ferroelectric layer. The ferroelectric capacitor can be provided as part of a memory cell of a ferroelectric memory.

Ferroelectric memory and ferroelectric capacitor with Ir-alloy electrode or Ru-alloy electrode and method of manufacturing same

A memory device and method for operating the same are provided. The example method may be directed to a method of performing a memory operation on a memory device, and may include applying a negative voltage bias to the memory device during a programming operation of the memory device and applying a positive voltage bias to the memory device during an erasing operation of the memory device. The example memory device may include a substrate and a gate structure formed on the substrate, the gate structure exhibiting a faster flat band voltage shift under a negative voltage bias than under a positive voltage bias, the gate structure receiving a negative voltage bias during a programming of the memory device and receiving a positive voltage bias during an erasing operation of the memory device.

Memory device and method for operating the same

A multi bits flash memory device and a method of operating the same are disclosed. The multi bits flash memory device includes: a stacked structure including: a first active layer with a mesa-like form disposed on a substrate; a second active layer, having a different conductivity type from the first active layer, formed on the first active layer; an active interlayer isolation layer interposed between the first active layer and the second active layer such that the first active layer is electrically isolated from the second active layer; a common source and a common drain formed on a pair of opposite side surfaces of the stacked structure; a common first gate and a common second gate formed on the other pair of opposite side surfaces of the stacked structure; a tunnel dielectric layer interposed between the first and second gates and the first and second active layers; and a charge trap layer, storing charges that tunnel through the tunnel dielectric layer, interposed between the tunnel dielectric layer and the first and second gates.

Multi bits flash memory device and method of operating the same

A magnetic memory device includes a plurality of first metal lines arranged in parallel on a substrate and including a plurality of magnetic domains with variable magnetization directions. A plurality of second metal lines is arranged on the substrate perpendicular to the first metal lines. The plurality of second metal lines each has a tunnel through which the plurality of first metal lines pass. First input units are connected to the plurality of first metal lines and supply a current to drag or move the plurality of magnetic domains. Second input units are connected to the plurality of second metal lines to supply a current for switching the magnetization directions of magnetic domains inside the tunnels. Sensing units are connected to the plurality of second metal lines for sensing an electromotive force caused by magnetic domain walls passing through the tunnels.

Magnetic memory device with moving magnetic domain walls

Disclosed are a multi-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the multi-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper surface of the semiconductor substrate; a plurality of storage nodes disposed on opposite sides of the channels perpendicularly the upper surface of the semiconductor substrate; a control gate surrounding upper portions of the channels and the storage nodes, and side surfaces of the storage nodes; and an insulating film formed between the channels and the storage nodes, between the channels and the control gate, and between the storage nodes and the control gate.

Multi-bit non-volatile memory device, method of operating the same, and method of manufacturing the multi-bit non-volatile memory device

Provided is a method for determining a zeta potential generated between a solid wall and a solution. The method includes (a) injecting an electrolyte solution into a first inlet of a T channel, which is provided with first and second inlet electrodes and a grounded outlet electrode, and a mixed solution of the electrolyte solution and a fluorescent dye into a second channel of the T channel and maintaining a steady-state of the two solutions; (b) applying a direct current electric field from the first and second electrodes to the outlet electrode to form an interface between the electrolyte solution and the mixed solution; (c) applying an alternating current electric field from one of the two inlet electrodes to the outlet electrode to oscillate the interface; and (d) measuring an amplitude of oscillation of the interface and determining the zeta potential from the standard relationship between the zeta potential and the amplitude.

Method and apparatus for determining zeta potential using alternating current electric field and T channel

Growing community of inventors

Seoul, South Korea

Sang-min Shin