Samsung Electronics Co., Ltd.

Sang-Kyu Kang

Jong-Hyun Choi

Hye-Jin Kim

Kyu-Chan Lee

Dong-Yang Lee

Dong-min Kim

Dong-hyun Sohn

Seung-Woo Ryu

Kwanghyun Kim

Jieun Shin

Haewon Lee

Ji Hyun Ahn

Doo-Hee Hwang

Ho-Cheol Bang

Jungbae Lee

Jae-Yeon Choi

DongMin Kim

Do Kyun Kim

A memory system is included in a host device. The memory system incudes: a volatile memory device that performs self-refresh until the host device turns on duty when detecting that the host device is off duty; a non-volatile memory device; and a processor that controls a read operation or a write operation of the volatile memory device and the nonvolatile memory device. The processor backs up data stored in the volatile memory device to the non-volatile memory device after a first time period elapses from when the host device is off duty. The volatile memory device stops the self-refresh after a second time period elapses from a time point when the data stored in the volatile memory device is backed up to the nonvolatile memory device.

Memory system reducing standby power and method for reducing standby power thereof

In some embodiments, a memory system includes a memory device and a host configured to transmit, to the memory device, a command and address (C/A) signal and a clock signal, and to transmit or receive data signals to or from the memory device. Each command that is configured to access the memory device is associated with an access timing parameter. The memory device includes an access parameter timer configured to measure an actual timing value of the access timing parameter, a spec register configured to provide a spec timing value defining an effective timing of the access timing parameter, a comparison circuit configured to compare the actual timing value and the spec timing value, and a mode register configured to store an access timing violation flag that is read by the host when the actual timing value deviates from the spec timing value by exceeding a predetermined range.

Memory device, memory system and method for operating memory system

A memory device includes a first volatile memory chip that includes a first volatile memory cell array storing first data and that receives or outputs the first data at a first bandwidth, and a second volatile memory chip that includes a second volatile memory cell array storing second data and that receives or outputs the second data at a second bandwidth different from the first bandwidth.

Memory device including heterogeneous volatile memory chips and electronic device including the same

A memory device includes a first data buffer receiving data of a first frequency band or a second frequency band, a first clock buffer providing a clock signal of the first frequency band to the first data buffer when the first data buffer receives the data of the first frequency band and providing a clock signal of the second frequency band to the first data buffer when the first data buffer receives the data of the second frequency band, a second data buffer receiving the data of the first frequency band or the second frequency band and receiving the clock signal of the second frequency band from the first clock buffer in response to receiving the data of the second frequency band, and a second clock buffer providing the clock signal of the first frequency band to the second data buffer in a first frequency band operation.

Memory device and a clock distribution method thereof

A semiconductor memory device includes a memory cell array including a plurality of bank arrays and a control logic circuit. The control logic circuit controls access to the memory cell array in response to a command and an address. A first number of memory cells are coupled to a bit-line of a first bank array of the plurality of bank arrays, a second number of memory cells are coupled to a bit-line of a second bank array of the plurality of bank arrays and the first number is different from the second number.

Semiconductor memory devices with banks with different numbers of memory cells coupled to their bit-lines and memory systems including the same

A semiconductor memory device includes a memory cell array and a control logic circuit. The control logic circuit controls access to the memory cell array based on a command and an address. The semiconductor memory device performs a write operation to write data in the memory cell array and performs a read operation to read data from the memory cell array in synchronization with a clock signal from an external memory controller. The semiconductor memory device performs the write operation and the read operation in different data strobe modes in which the semiconductor memory device uses different numbers of data strobe signals according to a frequency of the clock signal.

Semiconductor memory devices and methods of operating the same

A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode.

Semiconductor memory devices, memory systems including refresh control circuit and method of performing weak refresh operation on the weak pages thereof

A MRAM includes a memory cell array of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells. A source line voltage generator generates a source line driving voltage in response to an external power supply voltage and provides the source line driving voltage to the source line.

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Anyang-si, South Korea

Sang-Kyu Kang