Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Sang-Kuk Kim

Jongchul Park

Jong-Kyu Kim

Woohyun Lee

Yil-hyung Lee

Jongsoon Park

Inho Kim

Oik Kwon

Hyeji Yoon

Chul-Ho Shin

Gwang-Hyun Baek

Yeonji Kim

Hye-Ji Yoon

Jun-Sang Park

Seung-hoon Lee

Dong-Seok Lee

Jong-Chul Park

Keun-Hee Bai

Weon-Jun Choe

Jung-Ik Oh

Moon-Sang Hwang

Do-Haing Lee

Yoo-Chul Kong

Shin-hye Kim

Woo-Hyun Lee

O Ik Kwon

Kwangyoung Oh

Tokashiki Ken

Yunseung Kang

Yun Seung Kang

Jong-Soon Park

Tai-Ji An

Won-Kang Kim

Sujin Jeon

Hye Ji Yoon

Tae Hyung Lee

Su Jin Jeon

A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.

Semiconductor memory devices and methods for fabricating the same

A three-dimensional (3D) semiconductor memory device including first cell stacks arranged in first and second directions; second cell stacks disposed on the first cell stacks and arranged in the first and second directions; first conductive lines extending in the first direction and provided between a substrate and the first cell stacks; common conductive lines extending in the second direction and provided between the first and second cell stacks; etch stop patterns extending in the second direction and provided between the common conductive lines and top surfaces of the first cell stacks; second conductive lines extending in the first direction and provided on the second cell stacks; and a capping pattern covering a sidewall of the common conductive lines and a sidewall of the etch stop patterns, wherein each of the common conductive lines has a second thickness greater than a first thickness of each of the first conductive lines.

Three-dimensional semiconductor memory devices

A method of manufacturing a data storage device may include forming a magnetic tunnel junction layer on a substrate, irradiating a first ion beam on the magnetic tunnel junction layer to form magnetic tunnel junction patterns separated from each other, irradiating a second ion beam on the magnetic tunnel junction layer, and irradiating a third ion beam on the magnetic tunnel junction layer. The first ion beam may be irradiated at a first incident angle. The second ion beam may be irradiated at a second incident angle that may be smaller than the first incident angle. The third ion beam may be irradiated to form sidewall insulating patterns on sidewalls of the magnetic tunnel junction patterns based on re-depositing materials separated by the third ion beam on the sidewalls of the magnetic tunnel junction patterns.

Data storage devices and methods for manufacturing the same

An ion beam apparatus may include a chamber assembly configured to hold a material and direct an ion beam on the material, a detector configured to detect a signal generated from the material based on the ion beam being directed on the material, and a controller configured to control at least one parameter associated with the chamber assembly based on the signal, such that at least one of an ion energy associated with the ion beam, an ion current associated with the ion beam, and an incident angle of the ion beam with respect to a top surface of the material is changed continuously with time.

Ion beam apparatus with continuously changing parameter control

An etching target layer is formed on a substrate. An upper mask layer is formed on the etching target layer. A plurality of preliminary mask patterns is formed on the upper mask layer. The plurality of preliminary mask patterns is arranged at a first pitch. Two neighboring preliminary mask patterns of the plurality of preliminary mask patterns define a preliminary opening. An ion beam etching process is performed on the upper mask layer using the plurality of preliminary mask patterns as an etch mask to form a first preliminary-interim-mask pattern and a pair of second preliminary-interim-mask patterns. The first preliminary-interim-mask pattern is formed between one of the pair of second preliminary-interim-mask patterns and the other of the pair of second preliminary-interim-mask patterns.

Methods of fabricating semiconductor device

A magnetic memory device includes a lower interlayer insulating layer on a substrate, and a plurality of magnetic tunnel junction patterns on the lower interlayer insulating layer and isolated from direct contact with each other in a direction extending parallel to a top surface of the substrate. The lower interlayer insulating layer includes an upper surface including a recessed surface and a top surface, the recessed surface at least partially defining an inner sidewall and a bottom surface of a recess region between adjacent magnetic tunnel junction patterns, such that the recessed surface at least partially defines the recess region. The inner sidewall is inclined at an acute angle with respect to the top surface of the substrate, and the bottom surface has a shape that is convex toward the top surface of the substrate, in direction extending perpendicular to the top surface of the substrate.

Magnetic memory devices

A semiconductor device includes a first lower insulating interlayer, a protection insulating layer, and a first upper insulating interlayer that are sequentially stacked on a substrate, and a conductive pattern penetrating the first upper insulating interlayer, the protection insulating layer; and the first lower insulating interlayer. The conductive pattern includes a line part extending in a direction parallel to an upper surface of the substrate and contact parts extending from the line part toward the substrate. The contact parts are separated from each other with an insulating pattern therebetween. The insulating pattern includes a portion of each of the first upper insulating interlayer, the protection insulating layer, and the first lower insulating interlayer. At least a portion of the insulating pattern has a stepped profile.

Semiconductor devices

A digital-to-analog converter may include a converting unit and a distributing unit. The converting unit may generate a first analog signal set based on less-than-all bits of an image data set in a first period and may generate a second analog signal set based on all bits of the image data set in a second period. The all bits may include at least 2 bits. The distributing unit may include output terminals, may distribute the first analog signal set to the output terminals in a first sequence in the first period, and may distribute the second analog signal to the output terminals in a second sequence. The second sequence may be opposite to the first sequence.

Digital-to-analog converter, driving integrated circuit, and display device

Ion beam apparatuses and methods for forming patterns using the same, and methods for manufacturing magnetic memory devices using the same

Data storage devices are provided. A data storage device includes a dielectric layer on a substrate. The data storage device includes a plurality of data storage structures on the dielectric layer. The data storage device includes a conductive material on the dielectric layer. Moreover, the data storage device includes an insulation layer on the conductive material.

Data storage devices

Manufacturing an MRAM device may include forming an upper electrode on a magnetic tunnel junction stack, where the stack may include a lower electrode layer, a magnetic tunnel junction layer and a middle electrode layer that are sequentially formed on an insulating interlayer and a lower electrode contact on a substrate. The upper electrode may be formed on the middle electrode layer. An upper electrode protective structure may be formed to cover at least a sidewall and an upper surface of the upper electrode. The middle electrode layer, the magnetic tunnel junction layer and the lower electrode may be patterned by an etching process to form a middle electrode, a magnetic tunnel junction pattern and a lower electrode, respectively. The upper electrode protective structure may isolate the upper electrode from exposure during the patterning, and the upper electrode protective structure may remain on the upper electrode subsequently to the patterning.

Magnetoresistive random access memory devices and methods of manufacturing the same

In a method of forming a pattern of a semiconductor device, a first mask layer and an anti-reflective coating layer may be sequentially formed on a substrate. A photoresist layer may be formed on the anti-reflective coating layer. The photoresist layer may be exposed and developed to form a first preliminary photoresist pattern. A first ion beam etching process may be performed on the first preliminary photoresist pattern to form a second preliminary photoresist pattern. A second ion beam etching process may be performed on the second preliminary photoresist pattern to form a photoresist pattern. A second incident angle of an ion beam in the second ion beam etching process may be greater than a first incident angle of an ion beam in the first ion beam etching process. The anti-reflective coating layer and the first mask layer may be etched using the photoresist pattern as an etching mask to form a mask structure.

Method of forming patterns and method of manufacturing a semiconductor device using the same

A method for forming a pattern, the method including forming an etch target layer on a substrate; patterning the etch target layer to form patterns; and performing a pre-oxidation trim process a plurality of times, the pre-oxidation trim process including performing an oxidation process to form an insulating layer on a sidewall of each of the patterns; and performing a sputter etch process to remove at least a portion of the insulating layer.

Method for forming patterns and method for manufacturing magnetic memory device using the same

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Seongnam-si, South Korea

Sang-Kuk Kim