Samsung Electronics Co., Ltd.

Pantech Co., Ltd.

Sang-Keun Han

Hyuk-Joon Kwon

Bok-Yeon Won

Young-Wook Kim

Young-Ho Kim

Young-Ju Kim

Soo-Young Kim

Su-a Kim

Yong-Sik Kim

Hyun-chul Yoon

Ji-Suk Kwon

Ji-Hyung Kim

Woong-dai Kang

Bum-Jae Lee

Min-Woo Won

Ji-Hak Yu

Seok-Jae Lee

Jae-Man Hong

Hoo-Dong Lee

Chi-Hee Yun

A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

Sense amplifier having offset cancellation

A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

Memory device and method of disposing conduction lines of the same

Growing community of inventors

Seongnam-si, South Korea

Sang-Keun Han