Samsung Electronics Co., Ltd.

Sang-Jun Lee

Bong-Soo Kim

Youngjun Kim

Sang-Ho Lee

Sung-woo Park

Jung-Hyun Kim

Hyun-kyu Yun

Dae-Ho Choo

Kyunghyun Kim

Kwang-soo Kim

Je-min Park

Augustin Jinwoo Hong

Hyeon-Kyu Lee

Mong-sup Lee

Hyo-Dong Ban

Yoon-Chul Cho

Yoon-ho Son

Yong-Joon Kwon

Young-Ju Lee

Joon-Yong Choe

Pyeong-Hwan Wee

Inseak Hwang

Sungwoo Kim

Jungwoo Song

Jinhyung Park

Hyeran Lee

Mongsup Lee

Jae-Yeong Kwon

Ho-Ju Song

Young-Hak Choi

Yoonho Son

Yongjun Kim

Jaerok Kahng

Seok-Hyun Kim

Keeshik Park

Donggyun Han

Joon Young Kang

Jee-Hoon Ka

Munkwon Kang

Hee-Seob Ryu

A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

Memory devices and methods of manufacturing the same

A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.

Semiconductor memory device and a method of fabricating the same

Methods of manufacturing devices including a buried gate cell and a bit line structure including a thermal oxide buffer pattern

A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.

Method of manufactuing semiconductor device

A memory device includes a substrate including active areas and isolation areas, trenches in the isolation areas, active patterns in the active areas, the active patterns protruding from the substrate, isolation layers filling the trenches, gate trenches crossing the active patterns and the isolation layers, and gate line stacks filling the gate trenches, a first width of the gate trench in the isolation layer being greater than a second width of the gate trench in the active pattern.

Memory device having buried gate and method of fabricating the same

Method of manufacturing semiconductor device

A substrate having an insulating layer including an oxide is loaded into a chamber, and at least a part of the insulating layer is removed by injecting a process gas including an etching source gas into the chamber. The removal process is performed in a pulse type in which a first period and a second period are repeated a plurality of times. The etching source gas is supplied at a first flow rate during the first period and is supplied at a second flow rate less than the first flow rate during the second period. A temperature of the inside of the chamber remains at 100&#xb0; C. or more during the removal process.

Method of manufacturing semiconductor devices

An operating method, a base station, and terminal of a cell of a first communication system for a handover between the first communication system and a second communication system are provided. The method includes, receiving, by the base station, a measurement report including measured signal quality, from a terminal, determining, by the base station, a handover initiation to a target radio access network, based on the measured signal quality, transmitting, by the base station, a handover request message to the target radio access network via a core network, receiving, by the base station, radio-related information that is required if the terminal accesses the target radio access network, from the target radio access network via the core network, and transmitting, by the base station, the radio-related information of the target radio access network, to the terminal, wherein the handover between the source radio access network and the target radio access network comprises an inter radio access technology (RAT) handover.

Apparatus and method for handover between a heterogeneous communication system and a broadband wireless communication system

An in-line system for fabricating a liquid crystal display-includes a sealer coating unit for coating a sealer onto a first substrate with a plurality of liquid crystal display cell regions, a liquid crystal injection unit for dropping a liquid crystal onto the first substrate coated with the sealer, and an assembly unit for assembling the first substrate with the second substrate. A sealer hardening unit hardens the sealer interposed between the first and the second substrate to thereby assemble the first and the second substrate with each other. A substrate cutting unit cuts the first and the second substrates along cutting lines through illuminating a laser beam along the cutting lines such that the first and the second substrates are severed into the liquid crystal display cell regions.

In-line system and method for manufacturing liquid crystal display

An in-line system for fabricating a liquid crystal display includes a sealer coating unit for coating a sealer onto a first substrate with a plurality of liquid crystal display cell regions, a liquid crystal injection unit for dropping a liquid crystal onto the first substrate coated with the sealer, and an assembly unit for assembling the first substrate with the second substrate. A sealer hardening unit hardens the sealer interposed between the first and the second substrate to thereby assemble the first and the second substrate with each other. A substrate cutting unit cuts the first and the second substrates along cutting lines through illuminating a laser beam along the cutting lines such that the first and the second substrates are severed into the liquid crystal display cell regions.

Growing community of inventors

Incheon, South Korea

Sang-Jun Lee