Samsung Electronics Co., Ltd.

Sang-Jun Kim

Joo-Hyung Lee

Jun-Young Ko

Sung-Dae Cho

Jae-Yong Park

A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer.

Method of fabricating semiconductor package

A semiconductor package utilizing insulating peripheral sealing portions and pattern leads and methods for manufacturing such semiconductor packages are provided. The semiconductor package includes a substrate on which a semiconductor chip is mounted. The substrate includes a plurality of substrate pads and the semiconductor chip includes a plurality of chip pads on an active surface. The semiconductor chip is surrounded by one or more peripheral sealing layers and conductive lead patterns are formed across the peripheral sealing layer(s) to connect the chip pads to corresponding substrate pads. The chip and lead patterns may be encapsulated and the substrate may also be provided with external connection structures such as solder balls to complete the package.

Growing community of inventors

Asan-si, South Korea

Sang-Jun Kim