Samsung Electronics Co., Ltd.

Sang-Jun Hwang

Hitoshi Okamura

Dae-hyun Chung

Min-Bo Shin

Dong-Jun Choi

A deserializer and method for deserializing data are disclosed. The method includes converting data from a serial data domain to a parallel data domain, detecting a comma related to the parallel data while the data is in the serial data domain, wherein conversion of the data from the serial data domain to the parallel data domain is made in relation to detection of the comma.

Deserializer, related method, and clock frequency divider

A semiconductor memory device input circuit including a clock selection portion. The clock selection portion receives an internal clock signal before a data strobe signal is enabled. The input circuit includes a plurality of input buffers, a clock selection circuit, a calibration circuit, and a plurality of data registers. The clock selection circuit receives a selection signal that is maintained at a first logic level for a predetermined time from the time when power is initially supplied and has a second logic level. The clock selection circuit selects a first clock signal and outputs the first clock signal as a second clock signal when the selection signal is maintained at the first logic level. The clock selection circuit selects the data strobe signal and outputs the data strobe signal as the second clock signal when the selection signal is maintained at the second logic level.

Growing community of inventors

Gwanak-gu, South Korea

Sang-Jun Hwang