Samsung Electronics Co., Ltd.

Lg Information & Communications, Ltd.

Sang-Jun Choi

Jung-hyun Lee

Hyung-jin Bae

Chang-Soo Lee

Yoon-Dong Park

Yool Kang

Chang-rok Moon

Chun-Geun Park

Dong-Won Jung

Jung-Chak Ahn

Suk-Pil Kim

June-mo Koo

Sung-ho Park

Dae-lok Bae

Bum-seok Seo

Young-bum Koh

Sang-Bong Bang

Chris Hong

Myoung-jae Lee

Young-Ju Kim

Chang-soo Lee

Eun-hong Lee

Deok-kee Kim

Kwang-Soo Seol

In-Kyeong Yoo

Hoon-sang Oh

Jong-cheol Shin

Duck-Hyung Lee

Eun-Kyung Park

Yu-jin Ahn

Hoon-Sang Oh

Sung-tae Choi

An image sensor includes a first substrate including a driving element, a first insulation layer on the first substrate and on the driving element, a second substrate including a photoelectric conversion element, and a second insulation layer on the second substrate and on the photoelectric conversion element. A surface of the second insulation layer is on an upper surface of the first insulation layer. The image sensor includes a conductive connector penetrating the second insulation layer and a portion of the first insulation layer. Methods of forming image sensors are also disclosed.

Image sensors

An image sensor and a method for fabricating the image sensor are provided. The method for fabricating the image sensor includes forming a first insulating layer on a semiconductor epitaxial layer having multiple pixel regions; patterning a portion of the semiconductor epitaxial layer and the first insulating layer in a boundary region between the pixel regions to form a trench; forming a buried insulating layer on the first insulating layer, filling the trench, the buried insulating layer having a planar top surface; forming a second insulating layer on the buried insulating layer; forming a first mask pattern on the second insulating layer, the first mask pattern defining an opening overlapping the trench; and performing an ion implantation process using the first mask pattern as an ion implantation mask to form a first type potential barrier region in a bottom of the trench.

Image sensor and method of fabricating the same

Image sensors and methods of manufacturing image sensors

Provided is a data recording medium having improved data recording/storage characteristics and with an improved structure to have a higher data storage capacity, and a method of recording and/or easing data using the same. The data recording medium may include a Cu electrode layer on a substrate, and a data recording layer formed of a compound including a metal and at least one non-metal selected from the group consisting of S, Se, and Te, on the Cu electrode layer. Data is recordable to or erasable from the data recording layer by changing the resistance of the data recording layer by diffusing Cu ions from the Cu electrode layer to the data recording layer or by erasing Cu ions from the data recording layer by diffusing Cu ions from the data recording layer back to the Cu electrode layer, according to a voltage pulse applied to the data recording layer.

Data recording medium for data storage and method of recording or erasing data using the same

Provided are a resistive random access memory device and a method of manufacturing the same. The resistive random access memory device includes a switching device and a storage node connected to the switching device, and the storage node includes a first electrode and a second electrode and a resistance change layer formed of CuO between the first electrode and the second electrode.

Storage node of a resistive random access memory device with a resistance change layer and method of manufacturing the same

The nonvolatile memory device includes at least one pair of first electrode lines, at least one device structure disposed between the at least one pair of first electrode lines and a dielectric layer disposed between the at least one device structure and the at least one pair of first electrode lines. The at least one device structure includes a second electrode line including a first conductive type semiconductor, a resistance changing material layer adjacent to the second electrode line, a channel adjacent to the resistance changing material layer and including a second conductive type semiconductor different from the first conductive type semiconductor and a third electrode line adjacent to the channel and including the first conductive type semiconductor.

Nonvolatile memory device

A multi-layer storage node, resistive random access memory device and methods of manufacturing the same are provided. The resistive random access memory device includes a switching structure and a storage node connected to the switching structure. The storage node includes a lower electrode, a first layer, a second layer, and an upper electrode that may be sequentially stacked. The first layer may be formed on the lower electrode and includes at least one of oxygen (O), sulfur (S), selenium (Se), tellurium (Te) and combinations thereof. The second layer may be formed on the first layer and includes at least one of copper (Cu), silver (Ag) and combinations thereof. The second layer may be formed of a material having an oxidizing power less than that of the first layer. The upper electrode may be formed on the second layer.

Multi-layer storage node, resistive random access memory device including a multi-layer storage node and methods of manufacturing the same

Example embodiments may provide resistive random access memory devices and/or methods of manufacturing resistive random access memory devices. Example embodiment resistive random access memory devices may include a switching device and/or a storage node connected to the switching device. The storage node may include a stack structure including a plurality of resistance change layers separated from one another and first and second electrodes each on a side wall of the stack structure. The resistance change layers may be connected to the first and the second electrodes in parallel and/or may have different switching voltages from each other.

Resistive random access memory device

Provided are a wire structure and a semiconductor device having the wire structure. The wire structure includes a first wire that has a first region having a width of several to tens of nanometers and a second region having a width wider than that of the first region.

Wire structure and semiconductor device comprising the wire structure

A capacitor and a method of fabricating the capacitor are provided herein. The capacitor can be formed by forming two or more dielectric layers and a lower electrode, wherein at least one of the two or more dielectric layers is formed before the lower electrode is formed.

Method for fabricating a three-dimensional capacitor

Resistive memory devices having at least one varistor and methods of operating the same are disclosed. The resistive memory device may include at least one bottom electrode line, at least one top electrode line crossing the at least one bottom electrode line, and at least one stack structure disposed at an intersection of the at least one top electrode line and the at least one bottom electrode line including a varistor and a data storage layer.

Resistive RAM having at least one varistor and methods of operating the same

Provided is a resistive random access memory (RRAM) device having a switching device and a storage node connected to the switching device, the storage node including a first electrode formed of a metal compound, the metal compound including metal with no more than a divalence and a metal compound having anions, a solid electrolyte layer formed on the first electrode, and a second electrode formed on the solid electrolyte layer.

Provided is an insulation layer patterning method employing a flowable oxide, which does not use a photo-resist. Also, an insulation layer pattern and display devices including the insulation layer are disclosed.

Insulating layer patterning method, insulating layer formed by the insulating layer patterning method, display device having the insulating layer

A nonvolatile variable resistance memory device may include a lower electrode; a stacked structure including a first Cu compound layer disposed on the lower electrode, and a second Cu compound layer disposed on the first Cu compound layer; and an upper electrode disposed on the second Cu compound layer.

Growing community of inventors

Yongin-si, South Korea

Sang-Jun Choi