Skhynix Inc.

Hynix Semiconductor Inc.

Sang Joon Lim

Bok Kyu Choi

Eul Chul Jang

Qwan Ho Chung

Ju Il Eom

Won Duck Jung

Sung Mook Lim

Sung Min Kim

Seung Hyun Lee

Woong Hee Lee

Sung Woo Han

Seong Cheol Kim

Jin Ho Bae

Hyeong Seok Choi

Kwon Whan Han

Chang Jun Park

Tac Keun Oh

Ha Na Lee

Il Hwan Cho

Jae Hoon Lee

Byung Jun Bang

Jong Woo Yoo

Juil Eom

Jin Hwan Song

A semiconductor package may include a chip disposed on a substrate, a conductive structure disposed on the substrate to include a conductive structure frame including a side surface facing at least one side surface of the chip and to include conductive structure fingers extending from the conductive structure frame toward an edge of the substrate, and an electromagnetic interference (EMI) shielding layer covering the chip and the conductive structure and contacting a side surface of an end of one or more of the conductive structure fingers.

Semiconductor packages having EMI shielding layers

Disclosed is a semiconductor package. The semiconductor package may include a substrate a semiconductor chip mounted over a surface of the substrate such that an active surface of the semiconductor chip faces the surface of the substrate. The semiconductor chip and substrate may be configured for shielding or scattering electromagnetic waves.

Semiconductor package having an electro-magnetic interference  shielding or electro-magnetic wave scattering structure

Semiconductor package having an electro-magnetic interference shielding or electro-magnetic wave scattering structure

A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface. The first and second semiconductor chips are stacked such that the first and second active surfaces face each other.

Semiconductor package having a redistribution line structure

Package substrates are provided. The package substrate may include a power line and a ground line on a first surface of a substrate body; a plurality of signal lines on the first surface between the power line and the ground line; and a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line. Related semiconductor packages are also provided.

Electrical characteristics of package substrates and semiconductor packages including the same

According to one embodiment, a semiconductor package includes a band stop filter, which includes: a transmission line pattern arranged on a package substrate; and a conductive stub pattern arranged along the transmission line pattern in a state of being separated from the transmission line pattern.

Package substrate with band stop filter and semiconductor package including the same

The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed.

Semiconductor package having substrate for high speed semiconductor package

A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

Wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield and a method for fabricating the same

A circuit board having a board body includes a via structure. The via structure includes a conductive connector passing through the board body and a conductive shield member surrounding at least a portion of the conductive connector. The shield member prevents distortion of a data signal applied to the conductive connector, and also intercepts electromagnetic waves generated by the conductive connector.

Circuit board having conductive shield member and semiconductor package using the same

Growing community of inventors

Icheon-si, South Korea

Sang Joon Lim