Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Sang Jine Park

Young-Hoo Kim

Yong Sun Ko

In Seak Hwang

Ji Hoon Jeong

O Sung Kwon

Kun Tack Lee

Seok-Gyu Lee

Seo Hyun Kim

Richard O Henry

Chong Kwang Chang

Lothar Doni

Yong Siang Tan

Oh Jung Kwon

An apparatus for processing a substrate includes a process chamber; a support which is placed inside the process chamber and supports the substrate; a fluid supplier which supplies fluid into the process chamber; and a controller configured to perform a compressing step to bring the fluid into a supercritical phase inside the process chamber, in which the compressing step includes a continuous first section and second section, the fluid supplier includes a first portion and a second portion, and the controller supplies the fluid into the process chamber at a first speed during the first section using the first portion, and supplies the fluid into the process chamber at a second speed higher than the first speed during the second section using the second portion.

Apparatus and method for processing substrate

A substrate drying apparatus includes; a drying chamber configured to load a substrate and including a lower chamber and an upper chamber above the lower chamber, a supply port configured to supply a supercritical fluid into the drying chamber and including a main supply port and a sub-supply port horizontally spaced apart from the main supply port, wherein the main supply port penetrates a center portion of the upper chamber, and a first buffer member coupled to the upper chamber, vertically separated from the sub-supply port, and vertically overlapping the sub-supply port, such that supercritical fluid vertically introduced into the drying chamber through the sub-supply port is impeded by the first buffer member to change a flow direction for the supercritical fluid.

Substrate drying apparatus and semiconductor device manufacturing method using same

A method of fabricating semiconductor devices includes sequentially forming a gate layer and a mandrel layer on a substrate, forming a first photoresist on the mandrel layer, forming a mandrel pattern by at least partially removing the mandrel layer using the first photoresist as a mask, forming a spacer pattern that comprises a first mandrel spacer located on a side of a first mandrel included in the mandrel pattern and a second mandrel spacer located on the other side of the first mandrel, forming a sacrificial layer that covers the first and second mandrel spacers after removing the mandrel pattern, forming a second photoresist including a bridge pattern overlapping parts of the first and second mandrel spacers on the sacrificial layer; and forming a gate pattern by at least partially removing the gate layer using the first and second mandrel spacers and the second photoresist as a mask.

Methods of fabricating semiconductor devices including support patterns

Semiconductor devices may include a field insulating layer that is on a substrate, a gate structure that is on the substrate and separated from the field insulating layer, a first spacer structure that is on sidewalls and a lower surface of the gate structure and is separated from the field insulating layer, and a second spacer structure that is on a part of an upper surface of the field insulating layer that is overlapped by the gate structure.

Semiconductor devices utilizing spacer structures

Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, sacrificial nitride spacers on opposing sidewalls of the gate electrode and source/drain regions, which are self-aligned to the sacrificial nitride spacers, on a semiconductor substrate. The sacrificial nitride spacers are selectively removed using a diluted hydrofluoric acid solution having a nitride-to-oxide etching selectivity in excess of one. In order to increase charge carrier mobility within a channel of the field effect transistor, a stress-inducing electrically insulating layer is formed on opposing sidewalls of the gate electrode. This insulating layer is configured to induce a net tensile stress (NMOS) or compressive stress (PMOS) in the channel.

Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers

A patterned anti-reflective coating may be used as a selective implant-blocking layer during fabrication of an integrated circuit transistor. In particular, the anti-reflective coating may be used as a gate sidewall spacer to block at least some dopants from an integrated circuit substrate beneath the gate sidewall spacer. Moreover, a single mask may be used when fabricating source and drain extension regions and source and drain regions of an integrated circuit transistor.

Growing community of inventors

Suwon-si, South Korea

Sang Jine Park