Samsung Electronics Co., Ltd.

International Business Machines Corporation

Infineon Technologies Ag

Chartered Semiconductor Manufacturing Ltd (corporation)

Sang-Jine Park

Bo-un Yoon

Kee-Sang Kwon

Jeong-Nam Han

Do-hyoung Kim

Kyoung-hwan Yeo

Jae-Jik Baek

Keun-Hee Bai

Doo-Sung Yun

Yong-Ho Jeon

Kwang-Yong Yang

Byung-Kwon Cho

Ha-Young Jeon

Yeon-Jin Gil

Won-Sang Choi

Ji-Won Yun

Yong-Sun Ko

Ji-Min Jeong

Jin-wook Lee

Ji-Hoon Cha

Yong-Jhin Cho

Kwang-Wook Lee

Ki-Hyung Ko

Myung-geun Song

Kee-sang Kwon

Thomas W Dyer

Sunfei Fang

Young-Hoo Kim

Kun-Tack Lee

Min-ho Lee

Yoon-Hae Kim

Johnny Widodo

Ji-Hoon Jeong

Il-Young Yoon

Seung-Seok Ha

Young-sang Youn

Jun-jung Kim

Kevin Ahn

O-sung Kwon

Young-Sang Youn

A substrate processing apparatus includes a vessel providing a processing space for processing a substrate, a substrate support supporting the substrate loaded in the processing space, and a barrier between a side wall of the vessel and the substrate support and surrounding an edge of the substrate supported by the substrate support.

Substrate processing apparatus and apparatus for manufacturing integrated circuit device

Disclosed are a supercritical process chamber and an apparatus having the same. The process chamber includes a body frame having a protrusion protruding in an upward vertical direction from a first surface of the body frame and a recess defined by the protrusion and the first surface of the body frame; a cover frame; a buffer chamber arranged between the body frame and the cover frame; and a connector. The buffer chamber includes an inner vessel detachably coupled to the body frame providing a chamber space in the recess and an inner cover detachably coupled to the cover frame. The inner cover is in contact with a first surface of the inner vessel enclosing the chamber space from surroundings. The connector couples the body frame and the cover frame having the buffer chamber arranged therebetween such that the enclosed chamber space is transformed into a process space in which the supercritical process is performed.

Process chamber for a supercritical process and apparatus for treating substrates having the same

A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

Semiconductor device and method for fabricating the same

Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

Semiconductor devices including a dummy gate structure on a fin

An integrated circuit device includes an insulating film on a substrate, a lower wiring layer penetrating at least a portion of the insulating film, the lower wiring layer including a first metal, a lower conductive barrier film surrounding a bottom surface and a sidewall of the lower wiring layer, the lower conductive barrier film including a second metal different from the first metal, a first metal silicide capping layer covering a top surface of the lower wiring layer, the first metal silicide capping layer including the first metal, and a second metal silicide capping layer contacting the first metal silicide capping layer and disposed on the lower conductive barrier film, the second metal silicide capping layer including the second metal.

Integrated circuit device

A chemical supplier includes a chemical reservoir containing a chemical mixture at a room temperature, an inner space of the chemical reservoir being separated from surroundings, a supply line through which the chemical mixture is supplied to a process chamber from the chemical reservoir, an inline heater positioned on the supply line and heating the chemical mixture in the supply line to a process temperature, and a power source driving the chemical mixture to move the chemical mixture toward the process chamber.

Chemical supplier, processing apparatus including the chemical supplier

A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.

Methods of forming semiconductor devices including trench walls having multiple slopes

Semiconductor devices are provided. A semiconductor device includes a fin protruding from a substrate. Moreover, the semiconductor device includes first and second gate structures on the fin, and an isolation region between the first and second gate structures. The isolation region includes first and second portions having different respective widths. Related methods of forming semiconductor devices are also provided.

Semiconductor devices including an isolation layer on a fin and methods of forming semiconductor devices including an isolation layer on a fin

The semiconductor device may include an insulating interlayer on the substrate, the substrate including a contact region at an upper portion thereof, a main contact plug penetrating through the insulating interlayer and contacting the contact region, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern, and an extension pattern surrounding on an upper sidewall of the main contact plug, the extension pattern including a barrier material. In the semiconductor device, an alignment margin between the contact structure and an upper wiring thereon may increase. Also, a short failure between the contact structure and the gate electrode may be reduced.

Semiconductor devices including a contact structure and methods of manufacturing the same

Semiconductor devices are provided including a first active fin extending in a first direction and a second active fin spaced apart from the first active fin in a second direction perpendicular to the first direction, the second active fin extending in the first direction, the second active fin having a longer side shorter than a length of a longer side of the first active fin. A first dummy gate extends in the second direction overlapping a first end of each of the first and second active fins. A first metal gate extends in the second direction intersecting the first active fin and overlapping a second end of the second active fin. A first insulating gate extends in the second direction intersecting the first active fin. The first insulating gate extends into the first active fin.

Semiconductor devices including insulating gates and methods for fabricating the same

A first protective layer, a mask layer, a second protective layer and a photoresist layer are sequentially formed on a substrate. A photoresist pattern is formed by partially removing the photoresist layer. An ion implantation mask is formed by sequentially etching the second protective layer, the mask layer and the first protective layer using the photoresist pattern. The ion implantation mask exposes the substrate. Impurities are implanted in an upper portion of the substrate exposed by the ion implantation mask.

Methods of manufacturing semiconductor devices

Growing community of inventors

Yongin-si, South Korea

Sang-Jine Park