Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Sang-Jin Jeon

Min-Wook Park

Jeong-Young Lee

Se-Hwan Yu

Bum-Ki Baek

Sang-Ki Kwak

Kwon-Young Choi

Jang-Soo Kim

Hyang-Shik Kong

Seung-Soo Baek

Yong-Soon Lee

Jung-Joon Park

Han-Ju Lee

Min-cheol Lee

Hee-Bum Park

Sung-Man Kim

Jong-Hwan Lee

Il-Gon Kim

Bong-Jun Lee

Yeong-Keun Kwon

Beom-jun Kim

Hong-Woo Lee

Bon-Yong Koo

Yoon-Jang Kim

Ho-Kyoon Kwon

Se-Hyoung Cho

Gwang-Bum Ko

Yun-Hee Kwak

Jeong-Il Kim

Bae-Heuk Yim

Hee-Rim Song

Jun-Ki Jeong

A display apparatus includes a display panel including a driving part arranged along one side of the display panel, the display panel including a plurality of first gate lines that zigzag across the display in a diagonal direction between the first and second directions by alternately extending in the first and the second directions. The display device includes a first display area and a second display area, pixels within the first display area always receiving gate signals from a driving part connected to an end of the first gate lines. Within the second display area, a second gate lines extending in the first direction may be electrically connected to the first gate lines that relay gate signals to the first gate lines. This results in a reduced peripheral area of the display area, so that many displays can be combined together to produce a single image.

Display with gate lines in a diagonal direction

A gate drive circuit includes a shift register having a plurality of stages, in which an n-th stage ('n' is a natural number) of the plurality of stages is connected to at least one subsequent stage. The n-th stage includes a pull-up part configured to output a high voltage of an n-th gate signal using a high voltage of a clock signal as in response to a high voltage of a control node, a control pull-down part configured to pull-down a voltage of the control node into a low voltage in response to a carry signal outputted from at least one of next stages of the n-th stage and receiving a back-bias voltage corresponding to the low voltage, and a carry part configured to output the high voltage of the clock signal as an n-th carry signal in response to a high voltage of the control node.

Display apparatus having a gate drive circuit

A touch display substrate includes a first data line, a first gate line, a first pixel electrode, a second gate line, a second pixel electrode, a sensor data line and a first sensor electrode. The first data line extends along a first direction. The first gate line extends along a second direction. The first pixel electrode is electrically connected to the first data line and the first gate line. The second gate line is substantially parallel with the first gate line. The second pixel electrode is adjacent to the first pixel electrode and electrically connected to the first data line and the second gate line. The sensor data line is adjacent to the second pixel electrode and substantially parallel to the first data line. The first sensor electrode is electrically connected to the sensor data line.

Touch display substrate and touch display panel having the same

The present invention relates to a display device and a manufacturing method thereof. A display device according to an exemplary embodiment of the present invention includes a substrate including a first surface and a second surface, a first line disposed on the first surface and made of a transparent metal oxide semiconductor, and a first semiconductor disposed on the first surface and made of the transparent metal oxide semiconductor.

Display device and manufacturing method thereof

A display device may include an insulating substrate, a pixel electrode formed on the insulating substrate, a circuit board connected to the insulating substrate, a first wiring connected to the circuit board, and a second wiring for transmitting a signal to the pixel electrode. The second wiring may be connected to the first wiring, and the second wiring may have a larger resistance than the first wiring. Portions of the first wiring or the second wiring may include a zigzag pattern, and a swing width of a zigzag pattern of the second wiring may be varied depending on the position of the second wiring.

Display device having fanout wiring

In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.

Display panel and display apparatus having the same

A display device includes driving apparatus having first, second, third, and fourth gate drivers. The first and second gate drivers are connected to gate lines and are positioned on one side of the display device side by side. The third and fourth gate drivers are connected to gate lines and are positioned on the other side of the display device side by side. The first and third gate drivers apply the gate signal to the same gate line, and the second and fourth gate drivers apply the gate signal to the same gate line.

Driving apparatus of display device and display device including the same

A thin film transistor array panel comprises a repair line disposed in a peripheral area of a display area and being configured to repair when at least one of a gate line and a data line are disconnected, and a detour line disposed in the peripheral area and comprising at least one resistor having higher resistance than a remaining portion of the detour line, wherein both ends of the detour line are connected to the repair line to protect the array panel.

Thin film transistor array panel and method for manufacturing the same

A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Thin film transistor array panel and manufacturing method thereof

A method of driving gate lines is used to activate the gate lines by outputting output signals of stages to the gate lines. A first node is boosted up based upon a carry signal or the vertical start signal from a previous stage. A gate signal that is pulled up is outputted through an output terminal of a present stage based upon a first clock signal which is boosted up. An off-voltage is outputted through the output terminal of the present stage in response to an output signal from a next stage or the vertical start signal. The first node is discharged in response to the output signal from the next stage or a carry signal from a last stage. A positive ripple voltage at the first node is removed by providing a negative ripple voltage to the first node.

Method of driving gate lines, gate line drive circuit for performing the method and display device having the gate line drive circuit

A liquid crystal display that is subject to pixel-high defects due to manufacturing anomalies is provided with programmable repair means for each pixel electrode. In one embodiment, a transistor-array substrate is provided with plural gate lines that are separated from each other by a first interval, plural data lines that are insulated from the gate lines while crossing the gate lines, and separated from each other by a second interval larger than the first interval, thereby defining plural pixel areas. Each pixel area has a corresponding pixel unit comprising a switching device, pixel electrode, and repair electrode. The repair electrode branches from a neighboring gate line and extends such that the repair electrode is in overlapping spaced-apart relation with the pixel electrode and selectively connectable to the pixel electrode. Accordingly, a pixel where a high pixel defect occurs can be repaired by selective connection with the repair electrode, thereby improving display quality of the liquid crystal display.

Liquid crystal display having a defect repair mechanism interposed between a light shielding storage line and a light shielding output electrode

A device and corresponding method of fabrication thereof are disclosed, where the device provides a contact for semiconductor and display devices, the device including a substrate, a first wiring line assembly formed on the substrate, an under-layer formed on the first wiring line assembly, an organic insulating layer formed on the under-layer such that the organic insulating layer covers the under-layer, a pattern on the organic insulating layer for contact holes to expose the under-layer, etched contact holes formed in the under-layer in correspondence with the pattern such that the underlying first wiring line assembly is exposed to the outside, a cured organic insulating layer formed on the under-layer, and a second wiring line assembly formed on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the etched contact holes, and the corresponding method of fabrication including forming a first wiring line assembly on a substrate, forming an under-layer on the first wiring line assembly, forming an organic insulating layer such that the organic insulating layer covers the under-layer patterning the organic insulating layer to thereby form contact holes exposing the under-layer, etching the under-layer exposed through the contact holes such that the underlying first wiring line assembly is exposed to the outside, curing the organic insulating layer, and forming a second wiring line assembly on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the contact holes.

Contact for semiconductor and display devices

A panel for a display device includes a display area and a peripheral area. The display area comprises a plurality of pixels each comprising a switching element and gate lines and data lines connected to the pixels. The peripheral area comprises a plurality of gate driving integrated circuit regions, a plurality of data driving integrated circuit regions, a plurality of repair lines disposed along the edge of the panel, connecting pads connected to both ends of the repair lines, a test line connected to at least one connecting pad, and a test pad connected to the test line. A test method for detecting disconnection of the data lines is also provided.

Panel and test method for display device

A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Growing community of inventors

Suwon-si, South Korea

Sang-Jin Jeon