Electronics and Telecommunications Research Institute

Sang-Jin Byun

Hyun-Kyu Yu

Cheon-Soo Kim

A clock and data recovery apparatus reduces current consumption and enables easy integration. The inventive apparatus includes a first loop including a frequency/phase detection unit, a first charge pump unit, a multiplexing unit, a filtering unit, and a voltage controlled oscillator unit operating at a speed &#xbc; as fast as that of received data; a second loop having a phase detection unit operating at a speed &#xbc; as fast as a speed of received data, a second charge pump unit suitable for the phase detection unit, the multiplexing unit, the filtering unit, and the voltage controlled oscillator unit; a frequency lock detection unit for judging whether a frequency of a feedback clock signal falls within a desired frequency range; and a data recovery unit for recovering data from received data.

Clock and data recovery apparatus

Provided is a frequency lock detector which includes one counter and a clock number difference detector for detecting a clock number difference while not increasing complexity according to the counting number N to compare the frequencies of two clock signals whose phases are not synchronous to each other and determine whether the difference between the frequencies of the two signals is within a desired frequency accuracy. The frequency lock detector includes: a counter for counting the number of clocks of a reference clock signal inputted from outside; a clock number difference detector for detecting a difference between the clock number of the reference clock signal and the clock number of a recovered clock signal whose phase is not synchronous to the phase of the reference clock signal; and a lock determiner for determining a frequency lock based on result values of the counter and the clock number difference detector.

Frequency lock detector

Provided is an Inductor-Capacitor (LC) quadrature Voltage Controlled Oscillator (VCO) having a startup circuit which can accurately select one of +90&#xb0; and &#x2212;90&#xb0; as a phase difference between two clocks generated by the LC quadrature VCO by embodying the startup circuit therein by using a phase detector and a controller. The LC quadrature VCO includes a first LC tank for generating a second clock signal and a fourth clock signal, a second LC tank for generating a first clock signal and a third clock signal, a phase detector for receiving the clock signals from the first LC tank and the second LC tank, and detecting whether a phase difference between the clocks is +90&#xb0; or &#x2212;90&#xb0;, and a controller for discriminating whether phase information detected by the phase detector is equivalent to a phase difference between clocks required by the external signal processing unit, and changing an operation mode of the first LC tank and/or the second LC tank on the basis of the discrimination result of the phase difference between the clocks.

Growing community of inventors

Daejon, South Korea

Sang-Jin Byun