Skhynix Inc.

Hynix Semiconductor Inc.

Sang Jin Byeon

Jae Bum Ko

Tae Sik Yun

Sin Hyun Jin

Jae Jin Lee

Jong Chern Lee

Kyo Yun Lee

Sang Hoon Lee

Hyung Dong Lee

Dae Suk Kim

Young Jun Ku

Kee Teok Park

Jun Gi Choi

Sang Hoon Shin

An operating method of a memory device, comprising: entering self-refresh section, updating a counting code by counting an edge of a reference cycle signal, first activating an operation control signal for the self-refresh section when a temperature application code has an initialized value in response to the counting code, updating the temperature application code after the operation control signal is first activated, second activating the operation control signal in response to the counting code based on the updated temperature application code, exiting from the self-refresh section, and initializing the counting code and the temperature application code.

Memory device having stable self-refresh operation and operating method thereof

A method for operating a memory includes: receiving a predetermined command; performing an error check operation on a selected row and selected columns of one memory bank among a plurality of memory banks in response to the predetermined command; and performing a refresh operation on a selected row of each of the other memory banks among the memory banks in response to the predetermined command.

Memory, memory system and operation method of memory

A semiconductor apparatus includes a chip ID generation unit, a chip ID transmission unit and a chip stack information generation unit. The chip ID generation unit is configured to generate a chip ID signal. The chip ID transmission unit is configured to output the chip ID signal to a common line on the basis of whether another chip is electrically coupled therewith. The chip stack information generation unit is configured to be electrically coupled with the common line in response to the chip ID signal and generate a stack information signal.

Semiconductor apparatus and memory system

A semiconductor module may include a host, a first semiconductor device, and a second semiconductor device. The first host line may be connected to the first and second semiconductor device or devices, according to a set mode.

Semiconductor modules

A semiconductor apparatus may include a master chip, first to nslave chips, first to nslave chip ID generating units, and a master chip ID generating unit. The first to nslave chip ID generating units are disposed respectively in the first to nslave chips and connected in series to each other. Each of the first to nslave chip ID generating units is configured to add a predetermined code value to an moperation code to generate an (m+1)operation code. The master chip ID generating unit is disposed in the master chip to generate a variable first operation code in response to a select signal. Here, 'n' is an integer that is equal to or greater than 2, and 'm' is an integer that is equal to or greater than 1 and equal to or smaller than &#x2018;n&#x2019;.

Semiconductor apparatus

A data transmission circuit may include a first driving block configured to drive an output terminal for a first time in response to a data driving signal and a level of the output terminal, and a second driving block configured to drive the output terminal for a second time after the first time, in response to the data driving signal.

Data transmission circuit

A semiconductor memory apparatus includes an effective region which is a portion of the memory region and functions as a data storage space, a residual region which is another portion of the memory region, and a capacity control circuit which restricts supply of power and signals to the residual region.

Semiconductor memory apparatus

An operation mode setting circuit of a semiconductor apparatus includes a mode register set configured to update an operation mode information generated internally at the semiconductor apparatus based on preliminary information data in response to a preliminary information setting signal and a preliminary information providing block configured to provide the preliminary information data selected from a plurality of pre-stored preliminary information data to the mode register setting response to the preliminary information setting signal, the selected preliminary information data corresponding to a detected operation parameter detected in response to the preliminary information setting signal.

Operation mode setting circuit of semiconductor apparatus and data processing system using the same

A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

Semiconductor system having semiconductor apparatus and method of determining delay amount using the semiconductor apparatus

A semiconductor apparatus may include a first semiconductor chip; and a second semiconductor chip configured to transmit/receive signals to/from the first semiconductor chip. Further, a serializer/deserializer (SERDES) configured to serialize/deserialize input/output signals and a data bit inversion (DBI) logic electrically coupled to the SERDES and configured to perform a data inversion function on input/output data of the SERDES may be arranged in a preset region of any one of the first and second semiconductor chips.

Semiconductor apparatus and data bit inversion

A flip-flop circuit may include: a latch unit configured to latch an input signal in response to a clock signal; and a timing control unit configured to delay a signal provided from the latch unit by a predetermined time regardless of the clock signal.

Flip-flop circuit and semiconductor apparatus using the same

A power-up circuit of a semiconductor apparatus using a plurality of external power voltages is configured to determine a stableness of the plurality of external power voltages through relative comparison of the plurality of external power voltages, and to activate a power-up signal.

Power-up circuit of semiconductor apparatus

A semiconductor apparatus includes a control signal reception portion. The control signal reception portion may set information related to operation of a memory chip by receiving a command signal and an address signal from one among a stack chip test portion, a control signal interface portion and a test setting portion.

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Icheon-si, South Korea

Sang Jin Byeon