Hynix Semiconductor Inc.

Skhynix Inc.

Sang-Jin Byeon

Jae-Bum Ko

Jun-Gi Choi

Seok-Cheol Yoon

Khil-Ohk Kang

Beom-Ju Shin

Kang-Seol Lee

Jong-Chern Lee

Sin-Hyun Jin

Il Han Park

Jae-Jin Lee

Taek-Sang Song

Jae-Hyuk Im

Kee-Teok Park

Ki-Ho Kim

Tae-Yun Kim

A memory system includes: a memory device including a plurality of memory banks; and a memory controller suitable for monitoring a workload of the memory device and applying one of a first refresh command and a second refresh command to the memory device according to a result of the monitoring. In the memory device, the number of memory banks to be refreshed by the second refresh command may be greater than the number of memory banks to be refreshed by the first refresh command.

Memory controller and memory system including the same

A system includes: a master device; and a slave device including a temperature variation measuring circuit for measuring a temperature variation amount of the salve device for a predetermined time. The slave device transfers temperature information to a master device when a temperature variation amount for the predetermined time is equal to or greater than a threshold value, the temperature information representing that the temperature variation amount for the predetermined time is equal to or greater than the threshold value. The master device determines a temperature of the slave device in response to the temperature information, and controls the slave device based on the determined temperature of the slave device.

System including master device and slave device, and operation method of the system

A signal transmitting circuit may include: a logic gate coupled in series to transmit a signal, and operated by a first supply voltage; a pre-driver circuit suitable for generating a pull-up control signal and a pull-down control signal in response to the transmitted signal, wherein a second supply voltage having a level greater than the target level of the first supply voltage is used to generate the pull-up and pull-down control signals; a first NMOS transistor suitable for pulling up an output node using the first supply voltage, in response to the pull-up control signal; a second NMOS transistor suitable for pulling down the output node using a pull-down voltage, in response to the pull-down control signal; and an initialization circuit suitable for initializing the pull-up and pull-down control signals when the level of the first supply voltage is less than a reference value, before a power-up signal is enabled.

Signal transmitting circuit

A memory device includes a normal cell array, a parity cell array, and a plurality of normal write drivers suitable for writing normal write data in the normal cell array. The memory device also includes a plurality of parity write drivers suitable for writing parity write data corresponding to the normal write data, in the parity cell array, and an error injection circuit suitable for injecting error write data to at least one among the plurality of the normal write drivers and the plurality of the parity write drivers to exactly analyze an error of the memory device.

Memory device

A semiconductor package includes: memory devices that are stacked one on another; and an inter-layer channel for communication between the memory devices, wherein each memory device includes: a data pad; a memory core; a data input/output circuit that inputs/outputs data through the data pad; an inter-layer channel transfer circuit that transfers a read data transferred from the memory core to the inter-layer channel or transfers a data inputted through the data input/output circuit to the inter-layer channel; an inter-layer channel reception circuit receiving the data of the inter-layer channel; a read error correction circuit correcting an error of the data transferred from the inter-layer channel reception circuit to produce an error-corrected data and transfers the error-corrected data to the data input/output circuit; and a write error correction circuit generating a parity data to be stored in the memory core based on the data transferred from the inter-layer channel reception circuit.

Memory device transferring data between master and slave device and semiconductor package including the same

A memory system includes: a memory device suitable for performing a refresh operation in response to a refresh command, and for providing a refresh end signal where the refresh end signal is enabled before the refresh operation is completed; and a memory controller suitable for transferring the refresh command to the memory device and receiving the refresh end signal.

Memory device, memory system including the same, operation method of the memory system

An integrated circuit system comprising a first chip including a first period signal generation unit configured to generate a first period signal, transmit a first signal applied from a circuit outside of the integrated circuit system to a second chip, and transmit a second signal transmitted from the second chip to the circuit outside of the integrated circuit system, and the second chip including a second period signal generation unit configured to generate a second period signal, a code generation unit configured to generate codes corresponding to a difference between periods of the first period signal and the second period signal, and a delay unit configured to delay the second signal by using a delay value that is changed according to the codes.

Integrated circuit system and memory system

An integrated circuit chip includes a test circuit suitable for performing a test operation and generating a test result signal indicating whether there is an error or not in the integrated circuit chip, a transmitting unit suitable for transmitting the test result signal through an interlayer channel. The interlayer channel is precharged to a first level before the transmitting unit transmits the test result signal, and the interlayer channel is driven to a second level when there is an error.

Integrated circuit chip and multi-chip system including the same

A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units may transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device may be set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled.

Semiconductor device for parallel bit test and test method thereof

A semiconductor integrated circuit includes a plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a chip selection unit suitable for generating an internal chip selection signal in response to one or more selective chip selection signals and transferring the selective chip selection signals to an adjacent semiconductor chip of the plurality of semiconductor chips, a selective setting unit suitable for generating a selective internal signal, selectively activated in each semiconductor chip, in response to the internal chip selection signal and an external setting signal, and a common setting unit suitable for generating a common internal signal, activated in common in the plurality of semiconductor chips, in response to the setting signal and an external common chip selection signal.

Semiconductor integrated circuit

A memory chip includes a data processing block suitable for serial-parallel converting data inputted and for parallel-serial converting data to be outputted, a write data transmitting unit suitable for transmitting the data serial-parallel converted by the data processing block to a write data interlayer channel, a write data receiving unit suitable for receiving data from the write data interlayer channel, the data to be written to a core area, a read data receiving unit suitable for receiving data from a read data interlayer channel, the data to be parallel-serial converted by the data processing block, and a read data transmitting unit suitable for transmitting data read from the core area to the read data interlayer channel.

Memory chip and semiconductor package including the same

An integrated circuit system includes a first chip including a first node and configured to generate first identification information indicating the first chip in response to a voltage of the first node, a second chip including a second node and configured to generate second identification information indicating the second chip in response to a voltage of the second node, and a channel connected to the first node and the second node and generate a voltage difference between the first node and the second node.

Integrated circuit system including stacked chips for generating ID information

A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of the bit line sense amplification unit with an overdriving voltage in an overdriving period and supply an internal voltage line with a voltage of the power line of the bit line sense amplification unit in a discharge driving period.

Semiconductor device, semiconductor memory device and operation method thereof

A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.

Semiconductor integrated circuit and semiconductor system including the same

An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals.

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Gyeonggi-do, South Korea

Sang-Jin Byeon