Samsung Electronics Co., Ltd.

Sang-jib Han

Choong-Keun Kwak

Du-Eung Kim

Yun-Seung Shin

Chang-Rae Kim

Min-Chul Chung

Jong-Yul Park

Byung-Gil Choi

Sung-Bong Kim

Soon-moon Jung

An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory device selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory device. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory devices.

Integrated circuit capable of being burn-in tested using an alternating current stress and a testing method using the same

Disclosed is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks, a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks, a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed; said conjunction areas comprising one or more LA drivers adapted to drive block sense amplifiers, one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers, and-one or more BSYD circuits adapted to selectively enables LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining column and row block address decoding signals and simultaneously activating two or more BSYD circuits with the block control signals.

Method and apparatus for refreshing semiconductor memory

An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory cell selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory cell. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory cells.

Refresh-type memory with zero write recovery time and no maximum cycle time

A semiconductor memory device is disclosed. The device is comprised of a plurality of word lines; a plurality of bit lines arranged in perpendicular to the word lines. In addition, a plurality of supply voltage lines extend in the same direction as the bit lines. Also, a plurality of first ground voltage lines are arranged in the same direction as the bit lines. Further, a plurality of second ground voltage lines are arranged in the same direction as the word lines. A plurality of memory cells are each connected between one of the word lines and one of the bit lines. Here, the ground voltage lines are arranged in a matrix shape to reduce the resistance of the ground voltage line and secure the margin between the supply voltage level and the ground voltage level of the data latched by the memory cells to thereby prevent an operational failure of the device.

Static semiconductor memory device and fabricating method thereof

A semiconductor memory device includes a plurality of memory cell array blocks, an address transition detecting pulse generator to generate address transition detecting pulse signals by detecting the transition of a plurality of addresses, a global row decoder having a plurality of groups of pre-decoders and a main decoder to generate a plurality of global word line signals of a plurality of memory cell array blocks by decoding the plurality of addresses, and a plurality of block row decoders having a plurality of decoding cells to respond to block control signals for selecting a plurality of memory cell array blocks and a plurality of pulse control signals combined with the address transition detecting pulse signals to output a plurality of global word line signals generated by the global row decoder as a plurality of local word line signals. A plurality of the decoding cells of a plurality of the block row decoders comprises switching transistors or other means to switch the global word line signals into local word line signals in response to a first state of the pulse control signals, and inactive means, e.g. one or more transistors, to put the local word line signals into its inactive state in response to a second state of the pulse control signals, thereby reducing the number of transistors to make up of the decoder for efficient layout.

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Suwon, South Korea

Sang-jib Han