Samsung Electronics Co., Ltd.

Sansumg Electronics Co., Ltd.

Sang-Jib Han

Choong-Keun Kwak

Young-Ho Suh

Chang-Rae Kim

Chang-Hwan Lee

Min-Chul Chung

Hyung-Lae Eun

Jong-Yul Park

Byung-Jo Kim

Jai-kyeong Shinn

A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output pad, and a mode set circuit that may enable or disable the power voltage by a mode set signal in an individual chip test mode.

Multi-chip package semiconductor device and method of detecting a failure thereof

Provided is a semiconductor device package. The semiconductor device package includes: stacked semiconductor chips having bonding pads; a PCB (printed circuit board) mounting the stacked semiconductor chips thereon, and including bonding electrodes that correspond to the bonding pads; and interposers respectively covering the stacked semiconductor chips and interposed between the stacked semiconductor chips. The interposers comprise wire patterns connecting the bonding pads with the bonding electrodes, and connecting the interposers to each other.

Semiconductor device package

A semiconductor multi-chip package includes: a first semiconductor memory chip having n address pads, a first control pad, and a first address controller; and a second semiconductor memory chip whose memory density is greater, e.g., at least 1.5 times greater, than the first semiconductor memory chip and which is disposed on the first semiconductor memory chip, and has (n+1) address pads, a second control pad, and a second address controller. The n address pads of the first semiconductor memory chip and the n address pads of the second semiconductor memory chip are respectively connected to corresponding n address pins. The first and second control pads are connected to a control pin. The first and second address controllers are operable in a mutually exclusive manner, e.g., manner of activation, according to a signal applied to the control pin.

Semiconductor multi-chip package including two semiconductor memory chips having different memory densities

Integrated circuit devices are provided including first and second chips and a common input/output pad electrically coupled to the first and second chips. At least one of the first and second chips includes a high voltage generator configured to receive an input voltage through the common input/output pad and generate a test voltage responsive to a test mode signal during a test mode of operation. The test voltage is higher than the input voltage. Related methods of operating integrated circuit devices and semiconductor devices are also provided.

Multi-chip semiconductor packages and methods of operating the same

A semiconductor memory device and method for its operation are disclosed. The memory device uses refresh-type memory cells, but operates within the same timing parameters as a SRAM. A refreshing operation and a successful read/write operation can both be performed in a read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refreshing operations can also be performed during the read/write cycle. Thus the device operates with no maximum write cycle time limitation. In the disclosed method, an external write command causes the device to store the write address and data to registers instead of to the memory cell array. When the external write command signals that data is present, zero write recovery time is needed, since the registers require no address setup time. Because the memory cell array is not involved in this transaction, refresh operations can proceed as needed during the external write command, no matter how long the external write takes to complete. At a convenient time after the end of the external write command (e.g., during the next external write command), a short pulsed write operation transfers the data to the memory cell array.

Refresh-type memory with zero write recovery time and no maximum cycle time

A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

Growing community of inventors

Gyeonggi-do, South Korea

Sang-Jib Han