Samsung Electronics Co., Ltd.

Sang-Jae Rhee

Jae-Youn Youn

Jong-Ho Lee

Jae-Hoon Kim

Jong-Hyun Choi

Jung-Bae Lee

So-Young Kim

Uk-Song Kang

Kyu-Chan Lee

Soo-Young Kim

Joo-sun Choi

Yoon-jae Lee

Ki-Chul Chun

Jae-yoon Sim

Sang-Pyo Hong

Kwang-Sook Noh

Hyun-chul Yoon

Kyu-Chang Kang

Bok-Gue Park

Jin-Seong Kim

Yoon-Hwan Yoon

Min-Gyu Hwang

Jung-Yong Choi

Hyo-Chang Kim

Seung-Woo Hong

Chul-Min Lee

Dong-Gu Lee

Tae-Kyung Ko

Hyeong-Gon Son

Jong-Sik Na

A test method for a semiconductor device includes: loading a test tray having semiconductor devices of first and second lots arranged thereon into a test chamber; storing lot information of each of the semiconductor devices; performing a test program on each of the semiconductor devices; obtaining ID information of each of the semiconductor devices; matching the ID information with the lot information to generate lot sorting information; and sorting the semiconductor devices based on results of the test program and the lot sorting information.

Test method for semiconductor devices and a test system for semiconductor devices

A semiconductor memory device includes a memory cell array and a refresh control circuit. The refresh circuit is configured to: perform a second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation, and not perform the second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation. Whether the refresh control circuit performs or does not perform the second burst refresh operation is based on a comparison between an entering time for the self refresh operation of the memory cell rows and a reference time.

Semiconductor memory device performing a refresh operation, and memory system including the same

A semiconductor memory device and a self-refresh method of the semiconductor memory device. The semiconductor memory device includes: a memory cell array including one or more memory cells; a sense amplifier connected to a sensing line and a complementary sensing line and sensing/amplifying data stored in the one or more memory cells; and a sense amplifier control circuit sequentially supplying a first voltage and a second voltage having different levels to the sense amplifier through the sensing line during a refresh operation.

Semiconductor memory device and refresh method thereof

A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

Semiconductor memory device for byte-based masking operation and method of generating parity data

Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.

Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density

A semiconductor memory device having internal circuits responsive to temperature data, in order to compensate an output characteristic change of the internal circuits and reduce power consumption depending on temperature change, and method thereof are disclosed. The semiconductor memory device may include a temperature sensing circuit and an internal circuit. The temperature sensing circuit may generate and output temperature data in response to ambient temperature of the semiconductor memory device. The internal circuit may adjust an output level of an output signal in response to the temperature data from the temperature sensing circuit.

Semiconductor memory device having internal circuits responsive to temperature data and method thereof

An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.

Semiconductor memory device having an internal voltage generation circuit for selectively generating an internal voltage according to an external voltage level

In this circuit, an external voltage source is supplied or down converted in response to a normal operating mode to provide the internal voltage source of a first level to the internal circuit. The external voltage source is converted to a voltage of a second level, lower than the first level, in response to a low consumption power mode having a complementary relation with the normal mode.

Internal voltage source generator in semiconductor memory device

Semiconductor devices and methods of sampling data therefrom are provided in which data is sampled from a memory cell array based on a relative position of a memory cell array section that contains the data. A sense amplifier generates an output signal in response to an address of one or more cells in a memory cell array. A control circuit generates a sample control signal in response to at least a portion of the address (e.g., one or more high order bits of the address) of the one or more cells in the memory cell array. A data sampling circuit then samples the output signal of the sense amplifier in response to the sample control signal. The portion of the memory cell array address used to drive the control circuit may logically divide the memory cell array into two or more sections. The control circuit may adjust the timing of the sample control signal in accordance with the proximity of a memory cell array section to the sense amplifier.

Semiconductor memory devices and methods for sampling data therefrom based on a relative position of a memory cell array section containing the data

Output drivers preferably contain a plurality of driver circuits therein that are commonly connected to an output line to be driven and can be selectively enabled or disabled to increase or decrease drive capability, respectively. Driver circuits may include first and second control signal lines (e.g., MRS , MRS ), a first pull-up/pull-down driver circuit having first and second data inputs, a first control input electrically coupled to the first control signal line (e.g., MRS ) and a second control input, and a second pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit, respectively, a first control input electrically coupled to the second control signal line (e.g., MRS ) and a second control input. First and second complementary control signals lines (e.g., {overscore (MRS +L )}, {overscore (MRS +L )}) are also preferably provided and the second control inputs of the first pull-up/pull-down driver circuit and second pull-up/pull-down driver circuit are electrically coupled to the first and second complementary control signal lines, respectively. These control signal lines and complementary control signal lines can be used to control the number of driver circuits that are active within the output driver, based on loading conditions.

Integrated circuit memory devices having programmable output driver circuits therein

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Seongnam-si, South Korea

Sang-Jae Rhee