Samsung Electronics Co., Ltd.

Medison Co., Ltd.

Amolifescience Co., Ltd.

Kollodis Biosciences, Inc.

Sang-Jae Lee

Jun-Young Jeon

Jong-Wook Park

Gi-Won Cha

Myung-Gyoo Won

Chan Kim

In-Yong Seo

Hui-Gwan Goo

Dong-Sik Seo

Woo-Jung Lee

Jong-Won Byeon

Kyu-Won Baek

Seon-Ho Jang

Bong-Jin Hong

Song-Hee Koo

Seung-Hoon Lee

Ji-Hyun Lee

Sun-Soo Kim

Sung-Hyup Kim

The present disclosure relates to a three-dimensional micro-environment structure for controlling cell behavior, a three-dimensional surface and an array for controlling cell behavior, and a method for manufacturing the three-dimensional micro-environment structure.

Three-dimensional micro-environment structure for controlling cell behavior, three-dimensional surface for controlling cell behavior, and method for manufacturing array and three-dimensional micro-environment structure

A semiconductor integrated circuit device has a fuse device that can be electrically disconnected without a breakage caused by using a laser beam or current. The semiconductor integrated circuit device employs, as the fuse device for storing status information, a MOSFET of a single polysilicon EEPROM-type cell manufactured through a process of fabricating a volatile semiconductor memory cell array.

Integrated circuit having a non-volatile memory cell transistor as a fuse device

A portable ultrasonic diagnostic apparatus is provided. The portable ultrasonic diagnostic apparatus can be worn and carried on the shoulder, so that an activity for diagnosing a health condition of animals on the farm or open field can be put more simply and swiftly into practice. The portable ultrasonic diagnostic apparatus includes an ultrasonic diagnoser and a shoulder-wear member combined with the ultrasonic diagnoser so that the ultrasonic diagnoser can be put on the shoulder.

Portable ultrasonic diagnostic apparatus for veterinary activity

An integrated circuit memory device includes a memory cell block including a memory cell array which has a plurality of odd and even numbered subword lines extending therethrough. A first decoder is disposed at a top side of the memory cell block, which receives a first row address and generate a plurality of first control signals in response thereto. A second decoder is disposed at a bottom side of the memory cell block, which receives the first row address and generate a plurality of second control signals in response thereto. A row decoder receives a second row address and generates a word line signal in response thereto. A first driver block including a first plurality of subword line drive circuits adjacent to the memory cell array wherein each of the subword line drive circuits of the first plurality is connected to a respective odd numbered subword line of the memory cell array, and wherein the first plurality of subword line drive circuits drive the respective odd numbered subword lines responsive to odd numbered control signals of the first and the second control signals and the word line signal. A second driver block including a second plurality of subword line drive circuits adjacent to the memory cell array opposite to the first driver block wherein each of the subword line drive circuits of the second plurality is connected to a respective even numbered subword line of the memory cell array, and wherein the second plurality of subword line drive circuits drive the respective even numbered subword lines responsive to even numbered control signals of the first and the second control signals and the word line signal.

Integrated circuit memory device

An integrated circuit memory device includes a memory cell array including a plurality of odd and even numbered subword lines extending therethrough. A predecoder receives a row address and generates a plurality of predecoding signals in response thereto, and a row decoder receives the row address and generates a word line signal in response thereto. A first driver block includes a first plurality of word line drive circuits adjacent the memory cell array wherein each of the word line drive circuits of the first plurality is connected to a respective odd numbered subword line of the memory cell array. A first plurality of subword line drive circuits drive the respective odd numbered subword lines responsive to odd numbered predecoding signals and the word line signal. A second driver block includes a second plurality of word line drive circuits adjacent the memory cell array opposite the first driver block wherein each of the word line drive circuits of the second plurality is connected to a respective even numbered subword line of the memory cell array. The second plurality of subword line drive circuits drive the respective even numbered subword lines responsive to even numbered predecoding signals and the word line signal. Related methods are also disclosed.

Integrated circuit memory devices including split word lines and

Growing community of inventors

Seoul, South Korea

Sang-Jae Lee