Amkor Technology, Inc.

Sang Jae Jang

Choon Heung Lee

Chul Woo Park

Sung Su Park

Jae Dong Kim

Suk Gu Ko

Sun Goo Lee

Sung Soon Park

Seon Goo Lee

Akito Yoshida

Ki Wook Lee

Eun Sook Sohn

Chang Deok Lee

Jong Woon Choi

A semiconductor package comprises a plurality of stacked semiconductor chips having the same structure. Therefore, the semiconductor chips can be produced using masks of the same design, resulting in a reduction in production cost and an improvement in productivity. Each of the semiconductor chips includes a plurality of through-silicon vias penetrating therethrough. The through-silicon vias of each semiconductor chip include at least one signal pad through which a common signal is delivered to the semiconductor chip and at least one chip enable pad connected to at least one chip enable pin to select the semiconductor chip. The chip enable pin may be connected to or disconnected from the chip enable pad through a conductive line to select the semiconductor chip. The conductive line is sawn to disconnect the chip enable pin from the chip enable pad before stacking of the semiconductor chip. Therefore, the semiconductor chips can be configured to have the same design, thus eliminating the need for troublesome production management and control of the semiconductor chips.

Semiconductor device

In accordance with the present invention, there is provided multiple embodiments of a memory card, each embodiment including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto. The module is inserted into a complementary cavity formed within a case of the memory card, such case generally defining the outer appearance of the memory card. The module is secured within the cavity of the case through the use of an adhesive. In each embodiment of the present invention, the module is uniquely configured to prevent adhesive leakage from within the corresponding cavity of the case of the memory card when the module is secured within the cavity.

Modular memory card and method of making same

A memory card comprising a circuit board having opposed upper and lower circuit board surfaces, multiple side edges, a chamfer extending between a pair of the side edges, a plurality of pads disposed on the lower circuit board surface, and a conductive pattern which is disposed on the upper circuit board surface and electrically connected to the pads. At least one electronic circuit device is attached to the upper circuit board surface and electrically connected to the conductive pattern of the circuit board. A body at least partially encapsulates the circuit board and the electronic circuit element such that sections of the upper circuit board surface, including one which extends along the entirety of the chamfer, is not covered by the body.

Chamfered memory card module and method of making same

A memory card comprising a substrate having opposed top and bottom surfaces and a plurality of terminals disposed on the bottom surface thereof. Mounted to the top surface of the substrate is at least one component which is itself electrically connected to the terminals of the substrate. Formed on the bottom surface of the substrate is a first encapsulation part. Formed on the top surface of the substrate is a second encapsulation part which encapsulates the component mounted thereto.

Double mold memory card and its manufacturing method

In accordance with the present invention, there is provided multiple embodiments of a memory card, each embodiment including a case which is cooperatively engaged to a module comprising at least a printed circuit board having an electronic circuit device mounted thereto. In each embodiment of the present invention, the case is reinforced by a stiffener which effectively increases the mechanical strength of the fully fabricated memory card, thus providing the capability to withstand typical bending and twisting tests. The stiffener may be provided in any one of a plurality of different shapes or profiles, and may embedded within one or more of various locations within the case.

Enhanced durability memory card

A memory card including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto and at least one I/O pad and at least one test pad disposed thereon. The module is inserted into a complementary cavity formed within a case of the memory card, such case generally defining the outer appearance of the memory card. The module is secured within the cavity of the case through the use of an adhesive. In each embodiment of the present invention, first and second covers are movably attached to a case for selectively covering or exposing the I/O pads and the test features/pads of the module of the memory card.

Multiple cover memory card

A memory card comprising a circuit board having opposed upper and lower circuit board surfaces, at least one test pad disposed on the upper circuit board surface, and a conductive pattern disposed on the lower circuit board surface and electrically connected to the test pad. Electrically connected to the conductive pattern of the circuit board is a leadframe which includes a plurality of leads, each of the leads having a signal pad portion. At least one electronic circuit element is attached to the lower circuit board surface and electrically connected to the leadframe and to the conductive pattern of the circuit board. A body at least partially encapsulates the circuit board, the leadframe and the electronic circuit element such that the test pad of the circuit board is exposed in an upper body surface of the body, and the signal pad portions of the leads of the leadframe are exposed in a lower body surface of the body.

Memory card and its manufacturing method

A memory card comprising a die paddle having opposed, generally planar first and second die paddle surfaces and multiple peripheral edge segments. Disposed along and in spaced relation to one of the peripheral edge segments of the die paddle is a plurality of contacts, each of which has opposed, generally planar first and second contact surfaces. An inner body partially encapsulates the die paddle and the contacts, the first contact surface of each of the contacts and the first die paddle surface of the die paddle being exposed in and substantially flush with a generally planar first inner body surface of the inner body. The inner body further defines a generally planar second inner body surface which is disposed in opposed relation to the first inner body surface, the second contact surface of each of the contacts being exposed in the second inner body surface. At least one electronic circuit element is attached to the first die paddle surface and electrically connected to at least one of the contacts. An outer body partially encapsulates the inner body such that the first die paddle surface, the first contact surface of each of the contacts, the first inner body surface and the electronic circuit element are covered by the outer body, with the second inner body surface and hence the second contact surface of each of the contacts not being covered by the outer body and thus exposed.

An electrical substrate useful for semiconductor packages is disclosed. The electrical substrate includes a core insulative layer. A first surface of the insulative layer has circuit patterns thereon. Some of the circuit patterns are stepped in their heights from the first surface, in that a first subportion of the circuit pattern, including a ball land, extends further from the first surface than a second subportion of the same circuit pattern, and also extends further from the first surface than a ball land of other circuit patterns. Accordingly, solder balls fused to the ball lands of the stepped circuit patterns extend further from the first surface than same-size solder balls fused to the ball lands of the non-stepped circuit patterns, thereby circumventing electrical connectivity problems that may arise from warpage of the electrical substrate.

Semiconductor package structure reducing warpage and manufacturing method thereof

A semiconductor package has a substrate comprising a resin layer of an approximate planar plate, a cavity passing through the resin layer vertically at a center area thereof, a plurality of electrically conductive patterns formed at a bottom surface of the resin layer, and a conductive plan. An adhesive layer of a predetermined thickness is formed at an upper part of an inside of the cavity. A semiconductor die is positioned inside the cavity of the substrate and has a plurality of bond pads formed at a bottom surface thereof, a bottom surface of the adhesive layer being bonded to a top surface thereof. A plurality of conductive wires for electrically connecting the bond pads of the semiconductor die to the electrically conductive patterns are formed at a bottom surface of the substrate. An encapsulant is used for covering the semiconductor die formed at the lower part of the adhesive layer, the conductive wires and the cavity. A plurality of solder balls are fused to the electrically conductive patterns, which is formed at the bottom surface of the substrate.

Thin profile semiconductor package which reduces warpage and damage during laser markings

A stackable semiconductor package. The semiconductor package comprises a plurality of first and second leads which are arranged in a generally quadrangular array having one pair of opposed sides defined by the first leads and one pair of opposed sides defined by the second leads. The first and second leads each include opposed, generally planar first and second surfaces, and a third surface which is also disposed in opposed relation to the second surface and positioned between the first and second surfaces. A first semiconductor die is electrically connected to the third surfaces of the first leads, with a second semiconductor die being electrically connected to the third surfaces of the second leads. A package body at least partially encapsulates the first and second leads and the first and second semiconductor dies such that the first and second surfaces of each of the first and second leads are exposed in the package body.

Growing community of inventors

Gwangjin-gu, South Korea

Sang Jae Jang