Samsung Electronics Co., Ltd.

Sang-hyeon Lee

Dong-il Bae

Ki-nam Kim

Chang-Hyun Cho

Chang-hyun Cho

Yang-keun Park

Byung-Gook Kim

Dong-won Shin

Moon-gyu Sung

Hong-seok Sim

Jung-hwan Lee

Provided are photomasks, methods of fabricating the photomasks, and methods of fabricating a semiconductor device by using the photomasks, in which a critical dimension (CD) of a pattern of a specific region of the photomask is corrected to improve the distribution of CDs of the pattern formed on a wafer. The photomasks may include a substrate and a light-blocking pattern formed on the substrate that includes an absorber layer and an anti-reflection coating (ARC) layer. The light-blocking pattern may include at least one of a first corrected area in which a top surface of the absorber layer is exposed, and a second corrected area in which a correction layer is formed on the ARC layer.

Photomasks, methods of fabricating the photomasks, and method of fabricating semiconductor devices by using the photomasks

A method of repairing a photomask with a depression defect includes providing a photomask including a depression defect on a transparent substrate, forming a protection layer which covers the depression defect, etching a predetermined depth of the transparent substrate of the photomask with the protection layer as the etch mask, and removing the protection layer and the transparent substrate under the unetched protection layer, wherein a defect free photomask is produced.

Defect repair method for photomask and defect-free photomask

DRAM cells include a common drain region in an integrated circuit substrate and first and second source regions in the integrated circuit substrate, a respective one of which is laterally offset from the common drain region along respective first and second opposite directions. First and second storage nodes are provided on the integrated circuit substrate, a respective one of which is electrically connected to a respective one of the first and second source regions. The first and second storage nodes are laterally offset from the respective first and second source regions along the first direction.

Methods for fabricating dynamic random access memory cells having laterally offset storage nodes

Methods of forming field effect transistors having buried gate electrodes include the steps of forming a semiconductor substrate having a sacrificial gate electrode buried beneath a surface of the semiconductor substrate and then removing the sacrificial gate electrode to define a gate electrode cavity beneath the surface. The gate electrode cavity is lined with a gate insulating layer. The lined gate electrode cavity is filled with a first insulated gate electrode. A second insulated gate electrode is also formed on a portion of the semiconductor substrate extending opposite the first insulated gate electrode so that a channel region of the field effect transistor extends between the first and second insulated gate electrodes. Source and drain regions are also formed adjacent opposite ends of the first and second insulated gate electrodes.

Methods of forming MOS transistors having buried gate electrodes therein

A semiconductor device is manufactured by forming a first insulating layer on a semiconductor substrate. First contact pads and second contact pads are formed that penetrate through the first insulating layer and are electrically connected to the semiconductor substrate. A second insulating layer is formed that has guide contact holes that expose upper surfaces of the first contact pads. An etch stopper is formed on bottoms and sidewalls of the guide contact holes of the second insulating layer. Bit lines are formed that are electrically connected to the semiconductor substrate by the second contact pads. The bit lines are electrically isolated from the first contact pads.

Semiconductor devices having storage nodes

Dynamic random access memory cells having laterally offset storage nodes

Methods of manufacturing semiconductor devices having storage nodes

Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a drain region of the integrated circuit to provide a first concentration of ions in the first active area. Second ions are implanted into the first active area and a second active area of the substrate adjacent to the first active area and spaced-apart from the isolation structure on the substrate to provide a second concentration of ions in the second active area and a third concentration of ions in the first active area that is greater than the first and second concentrations. As a result, the level of ion concentration can be higher at the edge of an active channel region than at the center of the channel. The increased concentration of ions in the active area adjacent to the side wall of the trench may reduce a current between the source and drain regions of the transistor when voltage that is less than a threshold voltage of the transistor is applied to the gate electrode of the transistor. Thus, a reduction in the threshold voltage of the transistor can be inhibited. Integrated circuit transistors are also disclosed.

Devices with active areas having increased ion concentrations adjacent to isolation structures

Methods for manufacturing a storage node of a capacitor of a semiconductor device and a storage node manufactured by these methods are provided. An exemplary method for manufacturing a storage node of a capacitor of a semiconductor device includes forming a mold layer on a semiconductor substrate, forming a mold for the storage node by patterning the mold layer by a photolithography process, introducing a photomask which includes a plurality of light transmitting patterns separated from each other and which define the region to be occupied by the storage node, and forming a storage node that has the shape formed by the mold. The photolithography process is performed with the occurrence of a pattern bridge phenomenon, e.g., the transferred light transmitting patterns are connected to each other in a pattern transferred from the light transmitting patterns to the mold.

Growing community of inventors

Gyeonggi-do, South Korea

Sang-hyeon Lee