Samsung Electronics Co., Ltd.

Sang-Hune Park

Kwan-Yeob Chae

June-Hee Lee

Sang-Heon Lee

Jun-Ho Huh

In-Tae Kang

Ho-Rang Jang

Seok-Chan Kim

Jae-Chol Lee

Jin-Ho Choi

Jong-Ryun Choi

Hyung-Kweon Lee

Ji-hun Oh

Hyung-kweon Lee

Min-Ho Won

Dae-ro Kim

Seok-Kyun Ko

Sang-Hoon Joo

Hoon-Koo Lee

A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Modem and RF chips, application processor including the same and operating method thereof

A memory controller for receiving a differential data strobe signal and an application processor having the memory controller are disclosed. The memory controller includes a strobe signal receiver configured to receive first and second strobe signals from a memory device as differential data strobe signal and output a first detection signal based on a level of each of the first and second strobe signals, a comparator configured to receive the second strobe signal and a reference voltage and compare a level of the second strobe signal with a level of the reference voltage to output a second detection signal, and a gate signal generator configured to generate a gate signal masking a portion of a period corresponding to the differential data strobe signal using the first detection signal and the second detection signal.

Memory controller for receiving differential data strobe signals and application processor having the memory controller

A semiconductor device receiving a differential data strobe signal and a method of operating the same are provided. The semiconductor device includes a differential signal phase detector receiving a differential signal including a first signal and a second signal, detecting a phase of the differential signal, and generating a mode control signal; and a receiver receiving the differential signal and a reference voltage and performing a processing operation using the differential signal in a differential mode or using the first signal and the reference voltage in a single mode according to the mode control signal. The semiconductor device may be a memory controller. Data transfer may be disabled in the single mode to prevent false data recognition due to noise.

Semiconductor device and memory controller receiving differential signal

A delay cell includes first through fifth inversion circuits. The first inversion circuit inverts an input signal, and an output electrode of the first inversion circuit is coupled to a first node. The second inversion circuit is turned on in response to a control signal, and inverts the input signal when turned on. An output electrode of the second inversion circuit is coupled to the first node. The third inversion circuit inverts a signal at the first node, and an output electrode of the third inversion circuit is coupled to a second node. The fourth inversion circuit is turned on in response to the control signal, and inverts the signal at the first node when turned on. An output electrode of the fourth inversion circuit is coupled to the second node. The fifth inversion circuit inverts a signal at the second node to generate an output signal.

Delay cell and delay line having the same

A semiconductor device includes a driver circuit having an output resistance that is controllable responsive to a resistance control signal and a calibration circuit configured to duplicate a resistance behavior of the driver circuit and to generate the resistance control signal responsive to the duplicated resistance behavior. The driver circuit may include a first variable resistor and may be configured to couple an output node to a power supply node via the first variable resistor responsive to an input signal The calibration circuit may include a second variable resistor that is a duplicate of the first variable resistor. The calibration circuit may further include a current source circuit and may be configured to couple the second variable resistor between the power supply node and the current source circuit and to generate the resistance control signal responsive to a voltage of the second variable resistor.

Driver with resistance calibration capability

Growing community of inventors

Seongnam-si, South Korea

Sang-Hune Park