Micron Technology Incorporated

Sang-Hoon Shin

Won Joo Yun

Rajesh H Kariya

An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. A reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

Apparatus including reconfigurable interface and methods of manufacturing the same

An apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. An reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. The reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.

Test input/output speed conversion and related apparatuses and methods are disclosed. An apparatus includes a glue circuit and a BIST circuit for core circuitry of an integrated circuit device. The, the BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. The glue circuit is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glue circuit is configured to convert between second speed test interface signals and second speed input/output signals operating at a second speed and first speed test interface signals and first speed input/output signals operating at the first speed. The second speed is different from the first speed.

Test input/output speed conversion and related apparatuses and methods

Methods, systems, and devices for pattern generation for multi-channel memory array are described. A device may include a memory array and a circuit for testing the memory array. The memory array may include a first set of memory cells and a second set of memory cells, the first set of memory cells coupled with a first channel and the second set of memory cells coupled with a second channel. The circuit may be coupled with the memory array and may include a pattern generator and an output response analyzer. The pattern generator may be configured to selectively output a single pattern when operating in a single-pattern mode or a plurality of patterns when operating in a multi-pattern mode. The output response analyzer configured to determine whether the memory array includes one or more errors based at least in part on a pattern output by the pattern generator.

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Boise, ID, United States of America

Sang-Hoon Shin