Skhynix Inc.

Sang Hoon Shin

Keun Soo Song

Hyung Dong Lee

Jun Gi Choi

Seung Wook Kwak

Jeong Woo Lee

Xiang Hua Cui

Tae Yong Lee

Sang Jin Byeon

Kang Seol Lee

Tae Sik Yun

Young Suk Moon

Young Ju Kim

Chang Ho Lee

Young Hee Yoon

Hee Young Shin

Eun Jin Jung

Heyun Su Jang

A system for processing a wafer may use a wafer identification (ID) assigned by a wafer manufacturing company as an ID code of the wafer in managing the wafer by a semiconductor manufacturing company.

Wafer processing system and wafer processing method using same

A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.

Stack bank type semiconductor memory apparatus capable of improving alignment margin

A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via is charged by receiving an input voltage. The voltage driving unit generates a test voltage by charging or discharging the through via in response to a test control signal. The determination unit compares levels of the input voltage and the test voltage and outputs a resultant signal.

Test circuit and method of semiconductor integrated circuit

A semiconductor apparatus includes a memory chip which includes: a memory area; a data input/output block configured to communicate with the memory area; and a data transmission/reception block configured to connect one of a plurality of channels and a pad to the data input/output block, wherein the plurality of channels are configured to input and output normal data to and from another chip, and the pad is configured to input and output test data.

Semiconductor apparatus

A memory system includes: a controller configured to provide a hidden auto refresh command; and a memory configured to perform a refresh operation in response to the hidden auto refresh command. The controller and the memory communicate with each other so that each refresh address of the controller and the memory has the same value as each other.

Memory system

A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line.

Semiconductor integrated circuit

Various embodiments of a semiconductor apparatus are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a memory block chip and a signal input/output chip. The memory block chip is configured to control a data access size according to specifications. The signal input/output chip is configured to transmit input data from an external device to the memory block chip or transmit output data from the memory block chip to an external device and process the input data or the output data by selectively enabling a clock phase control unit and a signal processing unit according to the specifications.

A repair circuit of a semiconductor apparatus includes a plurality of through-silicon vias including repeated sets of one repair through-silicon via and an M number of normal through-silicon vias; a transmission unit configured to multiplex input data at a first multiplexing rate based on control signals, and transmit the multiplexed data to the plurality of through-silicon vias; a reception unit configured to multiplex signals transmitted through the plurality of through-silicon vias at a second multiplexing rate based on the control signals, and generate output data; and a control signal generation unit configured to generate sets of the control signals based on an input number of a test signal.

Repair circuit and repair method of semiconductor apparatus

A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.

Semiconductor memory apparatus and test method thereof

Provided is a semiconductor integrated circuit. The semiconductor integrated circuit comprises: a pair of interconnections; a fuse connecting the pair of interconnections; and one or more heat dissipation patterns connecting the pair of interconnections and are disposed around the fuse.

Growing community of inventors

Icheon-si, South Korea

Sang Hoon Shin