Samsung Electronics Co., Ltd.

National Cancer Center

Secugen Corporation

Samsung Sdi Co., Inc.

Sang-Hoon Shin

Kyo-Min Sohn

Hae-Suk Lee

Han-Vit Jung

Yong-Sik Park

Jong-Ho Kim

Suk-han Lee

Jae-Hoon Jung

Je-Min Ryu

Il-kwon Moon

Heon Yoo

Pyung-moon Zhang

Jae-Won Park

Ki-hyun Park

Ki-wang Kim

Seung-ho Ok

Young-Jae Kim

Sung-Ho Choi

Seung Hoon Lee

Kyung-Ho Kim

Ho-Young Song

Yong-Chan You

Chan-Kyung Kim

Sung-Ho Park

Dong Won Lee

Gil-Won Yoon

Tae-Woo Kim

In-duk Hwang

Woo-Young Jang

Kwang Gi Kim

Jae-chan Park

Hyun-Sung Shin

Ja-Choon Koo

Jeong-whan Lee

Yung-Ho Jo

Sang-Hyuk Lee

Jeong-Whan Lee

Hyouk-ryeol Choi

Byung-Jin Lee

Daniel Riley

Ho-seong Gi

Chan-ho Cho

Heung-Ki Jeon

Ho-Shin Gwak

Seung-Hoon Lee

Jin Soo Lee

A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.

Device and system including adaptive repair circuit

A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.

Memory device for adjusting memory capacity per channel and memory system including the same

A memory device includes a memory cell array formed in a semiconductor die, the memory cell array including a plurality of memory cells to store data and a calculation circuit formed in the semiconductor die. The calculation circuit performs calculations based on broadcast data and internal data and omits the calculations with respect to invalid data and performs the calculations with respect to valid data based on index data in a skip calculation mode, where the broadcast data are provided from outside the semiconductor die, the internal data are read from the memory cell array, and the index data indicates whether the internal data are the valid data or the invalid data. Power consumption is reduced by omitting the calculations and the read operation with respect to the invalid data through the skip calculation mode based on the index data.

Memory device supporting skip calculation mode and method of operating the same

A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Built-in self-test (BIST) circuit, memory device including the same, and method of operating the BIST circuit

A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters and perform a test on at least one memory core. The method includes setting a sweep range including a sweep start point of a first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

A skull implant medication injection port comprises: a mounted portion placed on an upper section of a port insertion hole in a patient's cranium and a medication inlet on a top surface; a medication injection diaphragm that seals the medication inlet of the mounted portion where a needle for injecting a medication is inserted; a medication storage portion coupled with a bottom of the mounted portion stores the medication injected through the medication injection diaphragm; a medication discharge pipe connected to the medication storage portion discharges the medication stored in the medication storage portion; and a rib formed on a perimeter between the mounted portion and the medication storage portion that has a diameter larger than an inner diameter of the port insertion hole. A height of the mounted portion is generally about 4 to 7 mm, and a height of the medication storage portion is generally about 2 to 4.2 mm.

Skull implant type medication injection port

A memory device including a stack semiconductor device including; an upper substrate vertically stacked on a lower substrate, the upper substrate including N upper through-silicon vias (UTSV) and upper driving circuits, and the lower substrate including N lower through-silicon vias (LTSV) and lower driving circuits, wherein each one of the upper driving circuits is stagger-connected between a Kth UTSV and a (K+1)th LTSV, where 'N' is a natural number greater than 1, and 'K' is a natural number ranging from 1 to (N&#x2212;1).

Stack semiconductor device and memory device with driving circuits connected to through-silicon-vias (TSV) in different substrates in a staggered manner

Methods and Apparatus are provided for fake fingerprint detection. In one embodiment, an apparatus for determining validity of a fingerprint includes a prism having an imaging surface configured to be touched by a fingerprint, one or more light sources configured to produce an image based on a refractive index of a material presented in association with the fingerprint, one or more imaging sensors configured to capture the image, and a controller configured to determine validity of the fingerprint based on whether the image has been masked.

Fake fingerprint detection system

Methods and Apparatus are provided for fake fingerprint detection. In one embodiment, an apparatus for fake fingerprint detection includes a prism having a first side configured to be touched by a fingerprint, an IR LED located near the second side of the prism, a light source located near the third side of the prism, where both the IR LED and the light source are configured to illuminate the fingerprint simultaneously to produce a captured image of the fingerprint, one or more lenses configured to direct the captured image of the fingerprint for storage, one or more CMOS sensors configured to collect the captured image of the fingerprint for analysis, and a controller configured to determine validity of the fingerprint using the captured image.

Method and apparatus for fake fingerprint detection

A device for and a method of measuring a blood flow of a living body having blood vessels that emit bio-photons and through which blood flows, the device including a detector positioned adjacent to a predetermined portion of the living body for measuring a bio-photon emission from the living body and a processor for analyzing and displaying the blood flow of the living body based on a value of the bio-photon emission.

Method of measuring blood flow using bio-photon emission

In a blood flow controlling apparatus using a magnetic field for controlling blood flow within a living body, and methods therefor, the blood flow controlling apparatus includes a magnetic field applying unit for supplying the magnetic field and applying the magnetic field to the living body, a blood flow measuring unit for measuring a blood flow signal including information about blood flow, and a blood flow controlling unit for controlling the blood flow according to the measured blood flow signal.

Apparatus for evaluating blood flow and controlling blood flow using a magnetic field and methods therefor

Growing community of inventors

Yongin-si, South Korea

Sang-Hoon Shin