Samsung Electronics Co., Ltd.

Sang-Hoon Jung

Ji Eun Kim

Chan Kim

Tae Seong Kim

Hyun Taek Jung

Jae Wook Joo

Ji Yean Kim

Jae-Youn Youn

Young-Sun Min

Seong-Jin Cho

Hyungkyu Kim

A memory device is provided. The memory device includes a plurality of memory chips that are stacked, wherein each of the memory chips includes a memory cell array, which includes a plurality of memory cell rows, a chip identifier generator configured to generate a chip identifier signal indicating a chip identifier of each of the memory chips, a refresh counter configured to generate a target row address for refreshing the memory cell rows in response to a refresh command, and a refresh row address generator, which receives the chip identifier signal and the target row address and outputs one of the target row address and an inverted target row address, obtained by inverting the target row address, as a refresh row address based on the chip identifier signal, and performs a refresh operation on a memory cell row corresponding to the refresh row address.

Memory device and semiconductor device including the same

Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.

Magnetic junction memory device and writing method thereof

A memory device includes a cell array including cells, an address transition detector outputting a transition detection signal as to whether an address of a write command is changed, and a control logic circuit generating one of word-line-on signals for performing a write operation on the cell array in response to the write command, and terminating the write operation in accordance with the transition detection signal. The word-line-on signals include a long-kept word-line-on signal that stays active before the address is changed and a divided word-line-on signal that is, before the address is changed, divided into sub-word-line-on signals.

Memory device having low write error rate

A memory device includes a first memory cell that is connected with a first source line, a first word line, and a first bit line, a first write circuit to receive first write data that are stored in the first memory cell through a first write input/output line and to control a voltage of the first source line and a voltage of the first bit line based on the first write data, and a first pull-down circuit to receive first pull-down data corresponding to the first write data from the first write circuit through a first internal metal line and to pulls down the voltage of at least one of the first source line and the first bit line to a predetermined voltage based on the first pull-down data.

Memory device

A memory device includes a first fail address register that stores a fail address, an input address register that stores an input address, a data comparison circuit that compares write data to be stored in a memory cell corresponding to the input address with read data read from the memory cell, an address comparison circuit that compares the fail address and the input address, and a second fail address register that stores bits of the fail address in parallel based on a first comparison result of the write data with the read data and a second comparison result of the fail address with the input address.

Memory device for preventing duplicate programming of fail address, and operating method thereof

A semiconductor memory device includes at least one sense amplifier, a controller and a sense amplifier driver. The sense amplifier includes a PMOS sense amplifier and an NMOS sense amplifier configured to be respectively activated in response to a first supply voltage and a second supply voltage, and to sense and amplify a voltage difference between a corresponding bit line pair. The controller is configured to set an operating mode in response to an external command, to control activation timing of a PMOS drive activation signal and an NMOS drive activation signal according to the set operating mode, and to output the PMOS drive activation signal and the NMOS drive activation signal. The sense amplifier driver is configured to apply the first and second supply voltages to the PMOS and NMOS sense amplifiers, respectively, in response to the PMOS drive activation signal and the NMOS drive activation signal.

Growing community of inventors

Hwaseong-si, South Korea

Sang-Hoon Jung