Electronics and Telecommunications Research Institute

Other

Korea Telecommunication Authority

Korea Telecom

Sang-Hoon Chai

Won-Chul Song

Hee-Bum Jung

Won-chan Kim

Jin-Hyo Lee

Hae-Wook Choi

Myung-Shin Kwak

Chang-Sik Yu

Hoon-Bock Lee

Mun-Yang Park

An improved data retiming circuit which is capable of more effectively retiming an externally inputted data by using a plurality of clocks from a voltage controlled oscillator of a phase-locked loop. The circuit includes a first delay unit for increasing a rising and falling time from an externally inputted data by a predetermined time as much as a clock phase difference, a first data latch unit connected so that the phase from the clock generator can be to correspond with the number of different clocks for latching the data inputted in accordance with the clock, a second delay unit for receiving the data from the first delay unit and for delaying the data so that a clock is selected and coincides with the timing until the output of the clock, a data latch state determination unit for determining the logic signal state of the data latched by the first data latch unit in an analog method, a clock selection unit for logically compares a plurality of clocks inputted and a data state signal outputted from the data latch state determination unit and for selecting a retiming signal, and a second data latch unit for latching the data relayed by the second delay unit in accordance with the retiming clock signal.

Data retiming circuit

A low power output buffer circuit for outputting an Emitter Coupled Logic(ECL) signal or Pseudo ECL(PECL) signal using a CMOS device is disclosed. The prior art differential output buffer circuit is comprised of two independent output buffer circuits and each output buffer circuit utilizes 50 ohms of the load resistors, having 20 mW of current to be applied to the circuit, which requires 100 mW of total consumptive power to operate the entire circuit. According to the present invention, a simplified output buffer circuit can be constructed by connecting 100 ohms of load resistors having a center tap to ground to two pads, which reduces half of the consumptive power as compared to that in the prior art circuit.

Low power output buffer circuit

Disclosed is a data and clock recovery circuit possible to restore data signals and synchronizing clocks which have been distorted during transmission over the communication line, which is comprised of the following: main oscillation loop that maintains operating frequency by using the input data and a self oscillation loop that operates using reference clock embedded within multiplex communication devices when communication lines get shorted or when power is restored after an outage; loop selecting switch which selects the main oscillation loop during normal operating mode and selects the self oscillation loop when communication line shorts or when the power is being restored; data signal monitor which connects to the loop selecting switch and determines communication line shorting by monitoring data transmission; power supply monitor which connects to the loop selecting switch and monitors the restoration of power after an outage. The circuit maintains stable operation and supplies stable output to multiplex communication devices not only during the normal operating conditions, but also when there is a communication line shorting or restoration of power after a power supply outage.

Data and clock recovery circuit

A method for making a semiconductor device having transistors comprising the active regions which are protected by polysilicon layer during the whole process from damages due to the other processing, that is dry etching, etc. and a minimized base region so as to provide a high operating speed and a minimium size thereof as well as lowest power consumption features.

Fabricating semiconductor device with polysilicon protection layer

Growing community of inventors

Daejeon, South Korea

Sang-Hoon Chai