International Business Machines Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Advanced Micro Devices Corporation

Kabushiki Kaisha Toshiba

Sony Computer Entertainment Inc.

Toshiba America Electronic Components, Inc.

Other

Globalfoundries Inc.

Sang Hoo Dhong

Joel Abraham Silberman

Osamu Takahashi

Harm Peter Hofstee

Wei Hwang

Hwa-Joon Oh

Silvia Melitta Mueller

Kevin John Nowka

Hung Cai Ngo

Brian King Flachs

Hyun J Shin

Cheng-Chung Lin

Takaaki Nakazato

Toru Asano

Toshiaki Kirihata

Dieter F Wendel

Nicky C Lu

Gilles Gervais

Ming-Zhang Kuo

James Douglas Warnock

Christian Jacobi

Lee-Chung Lu

Gary Bela Bronner

Brad William Michael

Hui-Zhong Zhuang

Matthew R Wordeman

Makoto Aikawa

Lewis M Terman

Tetsuji Tamura

Ping-Lin Yang

Nobuo Kojima

Li-Chun Tien

Ting-Wei Chiang

Philip George Emma

Ta-Pen Guo

William Robert Reohr

Michael Jay Shapiro

Jonathan James DeMent

Iwao Takiguchi

Kevin K Chan

Charles Ray Johns

Kirk David Peterson

David William Boerstler

Jean-Pierre Colinge

Chung-Cheng Wu

Shang-Chih Hsieh

Yoichi Taira

Jerry Chang Jui Kao

Chi-Lin Liu

John J Wuu

Hyun-Jin Cho

David Meltzer

Peichun Peter Liu

Toshio Sunaga

Terry I Chappell

Jung-Suk Goo

Michael Kevin Ciraula

John Samuel Liberty

Robert Louis Franch

Jin Haeng Cho

Louis Bernard Bushard

Mark S Milshtein

Jeffrey L Burns

Walter H Henkels

Young Hoon Lee

Louis L Hsu

Rajiv V Joshi

Jiann-Tyng Tzeng

Ravi Nair

William Vincent Huott

Alain F Loiseau

Li-Kong Wang

Jieming Qi

Atsushi Kawasumi

Eskinder Hailu

Jan Van Lunteren

Juergen Pille

Uttam Shymalindu Ghoshal

Thuong Quang Truong

David E Lackey

Mack Wayne Riley

Howard Hao Chen

Gordon Clyde Fossum

Yosuke Muraki

Barbara A Chappell

Leon Jacob Sigal

Uttam Shyamalindu Ghoshal

Tin-Chee Lo

Jeffrey Herbert Fischer

Robert Walter Berry, Jr

Byron Lee Krauter

Stephen Douglas Weitzel

Kazuhiko Miki

Rudolf Adriaan Haring

John Chester Malinowski

Yaping Zhou

Chorng-Lii Hwang

Chin-An Chang

Kin Shing Chan

Talal K Jaber

A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Semiconductor structure

A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.

System and method of timing characterization for semiconductor circuit

A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.

An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.

Integrated circuit with well and substrate contacts

A semiconductor arrangement includes a first semiconductor device including a first type region having a first conductivity type and a second type region having a second conductivity type. The semiconductor arrangement includes a second semiconductor device adjacent the first semiconductor device. The second semiconductor device includes a third type region having a third conductivity type and a fourth type region having a fourth conductivity type. The semiconductor arrangement includes a first insulator layer including a first insulator portion around at least some of the first semiconductor device and a second insulator portion around at least some of the second semiconductor device. The first insulator portion has a first insulator height, and the second insulator portion has a second insulator height. The first insulator height is different than the second insulator height. A method of forming a semiconductor arrangement is provided.

Semiconductor arrangement

One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment.

Scan cell assignment

An embodiment of a method of lithography includes generating a beam of electrons. A first pixel and a second pixel are each configured to pattern the beam. Using time domain multiplex loading, the first and second pixels are controlled such that the beam is patterned. The patterning includes receiving a first clock signal and using the first clock signal to generate a second clock signal and a third clock signal. The second clock signal is sent to the first pixel and sending the third clock signal is sent to the second pixel.

Electron beam lithography methods including time division multiplex loading

A clock regenerator includes a pulse generating module, a control logic module, a gating module and an output module. The pulse generating module is configured to receive a global clock signal and produce a periodic pulse signal triggered by a rising edge of the global clock signal. The control logic module is configured to receive a plurality of control signals and produce a pulse-type setting signal and a gating signal according to the periodic pulse signal and the control signals. The gating module is configured to produce an intermediate clock signal according to the pulse-type setting signal and the gating signal. The output module is configured to provide a local clock signal according to the intermediate clock signal.

Clock regenerator

A memory includes a word line, a bit line and a complementary bit line. A memory cell has a data node coupled to the bit line and a complementary data node coupled to the complementary bit line. The word line controls access to the memory cell. A circuit is coupled to the bit line and the complementary bit line. The circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving. The first timing and the second timing are synchronized.

Memory circuit for pre-charging and write driving

A system includes an integrated circuit (IC) design data base having a feature, a source configured to generate a radiation beam, a pattern generator (PG) including a mirror array plate and an electrode plate disposed over the mirror array plate, wherein the electrode plate includes a lens let having a first dimension and a second dimension perpendicular to the first dimension with the first dimension larger than the second dimension so that the lens let modifies the radiation beam to form the long shaped radiation beam, and a stage configured secured the substrate. The system further includes an electric field generator connecting the mirror array plate. The mirror array plate includes a mirror. The mirror absorbs or reflects the radiation beam. The radiation beam includes electron beam or ion beam. The second dimension is equal to a minimum dimension of the feature.

Charged particle lithography system with a long shape illumination beam

The present disclosure provides a systems and methods for e-beam lithography. One system includes an electron source operable to produce a beam and an array of pixels operable to pattern the beam. Control circuitry is spaced a distance from and coupled to the array of pixels. The control circuitry uses time domain multiplex loading (TMDL) to control the array of pixels.

Electron beam lithography systems and methods including time division multiplex loading

A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor.

Dynamic random access memory (DRAM) cells and methods for fabricating the same

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Austin, TX, United States of America

Sang Hoo Dhong