Hyundai Electronics Industries Co. Ltd.

Sang Hoan Chang

Ki Seog Kim

Keun Woo Lee

Jin Gwan Shin

Sung Kee Park

Keon Soo Shim

Seoung Ouk Choi

There is disclosed a method of monitoring a source contact in a flash memory by which whether a source contact having a narrow contact area contacts or not can be easily monitored using over-erase cell characteristic in a flash cell, in a flash memory device in which a source line is formed by a local interconnection method. In the present invention, in order to monitor a contact state at source contacts, the same voltage to the erase condition of a cell is applied to respective terminals (VG terminal, VD terminal, VS terminal and VSS terminal) wherein all the electrons existing at a floating gate in all the cells connected to the VS terminal and VSS terminal become turned on so that they can be over-erased. On the other hands, as electrons existing at the floating gate in two cells shared by any source contacts having a defect contact are not erased, the cells remain turn-off. In this state, if test voltages (VG&equals;0V, VD<5V, VS&equals;float, VSS&equals; ground) are applied, the current flow from the VD terminal to the VSS terminal is broken in the portion having a contact defect, thus allowing the contact state of the source contacts to be monitored.

Method of monitoring a source contact in a flash memory

There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a well resistance and a parasitic capacitance are great and the erase speed of a device is slow in case of the conventional flash memory device, the present invention forms a well region of a sector unit by use of a metal silicide layer and defines an unit cell by use of a ploysilicon layer. Thus, it can reduce the well resistance and the parasitic capacitance. Also, it can improve the operating speed of the device and can reduce the manufacturing cost by allowing the erase operation of a cell unit.

Method of manufacturing a flash memory device

There is disclosed a multi-bit flash memory cell and programming method using the same. In order to solve the problems that the size of a cell per unit is increased, reliability of a device is degraded due to a high operating voltage and a circuit necessary for driving the cell becomes complicated, the multi-bit flash memory cell and programming method using the same according to the present invention stores information of various states, by interchangeably programs a drain and a source in a cell array of virtual ground type, in a structure in which that two types of cells look like connected serially by doping a floating gate in a flash memory cell with two regions of a N type and a P to type.

Multi-bit flash memory cell and programming method using the same

A solid state memory according to the present invention comprises a plurality of memory chips; a confirmation circuit to confirm an input address by comparing said input address to each address latched to a latch circuit; a common serial bus for transmitting commands, addresses and data between the memory chips and the confirmation circuit; and a printed circuit board on which the memory chips and the confirmation circuit are mounted.

Growing community of inventors

Kyungki-do, South Korea

Sang Hoan Chang